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Eliminating Cycle-Slips in Phase-Locked Loop With D-Type Phase Detector

IP.com Disclosure Number: IPCOM000100854D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Boerstler, DW: AUTHOR

Abstract

The probability of cycle-slipping can be reduced in a phase-locked loop (PLL) incorporating a D-type phase detector under conditions of internal oscillator noise or input signal modulation by decreasing the filter ratio fzero/fpole, but this usually increases clock jitter. Disclosed is a technique for reducing cycle slipping by changing fpole and fzero, but leaving the ratio unchanged.

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Eliminating Cycle-Slips in Phase-Locked Loop With D-Type Phase Detector

       The probability of cycle-slipping can be reduced in a
phase-locked loop (PLL) incorporating a D-type phase detector under
conditions of internal oscillator noise or input signal modulation by
decreasing the filter ratio fzero/fpole, but this usually increases
clock jitter. Disclosed is a technique for reducing cycle slipping by
changing fpole and fzero, but leaving the ratio unchanged.

      Pullout frequency is used as the figure of merit of the loop's
tolerance to cycle-slipping, and is defined as the maximum frequency
error introduced into the loop for which cycle-slipping does not
occur.  The figure shows how pullout frequency is affected by the
filter ratio and the pole frequency of the PLL filter.  Once the
figure has been generated using the basic design parameters of the
PLL, the design may be optimized for resistance to cycle-slipping by
adjustment of the filter ratio and the pole frequency.

      The slope of the curve is equal to (A K M )/2, where A
is the normalized phase detector slope at zero phase error, K is the
loop gain, and M is an empirically derived constant dependent on A.
The y-intercept is equal to (( M Wp )/2) + (B SQRT (K Wp )),
where Wp is the pole frequency and B is an empirically derived
constant dependent on A.