Browse Prior Art Database

Improved Cost, Performance, And Reliability by Simultaneous Accesses to Pipelined Caches With Duplicate Data Protection And Enhanced Multipro Cessor Performance

IP.com Disclosure Number: IPCOM000100855D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+4]

Abstract

Two (private) caches, one larger and the other faster, are accessed simultaneously, the combination giving approximately the hit ratio of the larger cache but the cycle time of the faster cache. By writing to both caches simultaneously, and also by writing any modified data back to memory from the small cache (as it ages out), there is always a duplicate copy of any data located in cache. Copies must exist either in both of the two caches or in both the larger cache and in memory. When requested data is found in both the smaller and larger cache, the two copies may be compared (by saving the faster copy until the other arrives).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Improved Cost, Performance, And Reliability by Simultaneous Accesses to Pipelined Caches With Duplicate Data Protection And Enhanced Multipro Cessor Performance

       Two (private) caches, one larger and the other faster,
are accessed simultaneously, the combination giving approximately the
hit ratio of the larger cache but the cycle time of the faster cache.
By writing to both caches simultaneously, and also by writing any
modified data back to memory from the small cache (as it ages out),
there is always a duplicate copy of any data located in cache. Copies
must exist either in both of the two caches or in both the larger
cache and in memory.  When requested data is found in both the
smaller and larger cache, the two copies may be compared (by saving
the faster copy until the other arrives).  The reliability obtainable
(for those accesses where data is found in the smaller cache) can be
even better than with 8/13 Error Correction Code (ECC) using a
comparison that determines if the copies are different by more than
one bit.

      The cast out is more accurate if the smaller cache has a
smaller line size, potentially reducing the traffic back to memory,
making buffering easier, and improving the ability to interleave
memory traffic from the different sources.  Since traffic from memory
to cache is controlled by aging of the smaller cache, the traffic to
memory is slightly more even than in conventional systems.  The bits
of the smaller cache (plus parity on...