Browse Prior Art Database

Double Dense High Performance Zig-Zag In-Line Package

IP.com Disclosure Number: IPCOM000100858D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Dombroski, EJ: AUTHOR

Abstract

By containing two, single chip ZIPs (zig-zag in-line packages) within a dimensional envelope of size equal to conventional containment of a single ZIP, double chip density is achieved at the card assembly level.

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This is the abbreviated version, containing approximately 100% of the total text.

Double Dense High Performance Zig-Zag In-Line Package

       By containing two, single chip ZIPs (zig-zag in-line
packages) within a dimensional envelope of size equal to conventional
containment of a single ZIP, double chip density is achieved at the
card assembly level.

      Referring to the figure, circuit chip 2 is connected by wire
bonds 4 to external leads 6 and encased in a molded plastic 8 as is
usual in an area wire (A-wire) bond package. Chip 10 is also in an
A-wire molded package.  External leads 6 from chip 2 and leads 12
from chip 10 are formed so as to make like external leads from the
two packages touch or become proximate when the two chip packages are
joined by adhesive layer 14.  Chip select lead 16 from chip 2 and
chip select lead 18 from chip 10 are the only external leads which
are not made to be connected in parallel when all touching or
proximate leads are subsequently solder joined in a solder dip
process.

      To dissipate heat and/or to promote temperature equality at
adhesive and plastic package interfaces, a conductive sheet may be
adhesive bonded at the position of adhesive 14 in the figure and may
extend for a distance into air space around the package.