Browse Prior Art Database

Improved BIFET Circuit

IP.com Disclosure Number: IPCOM000100860D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 154K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

The circuits described herein are able to generate a full CMOS output voltage level transition, from VDD to ground potential.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Improved BIFET Circuit

       The circuits described herein are able to generate a full
CMOS output voltage level transition, from VDD to ground potential.

      The ability to integrate NPN bipolar transistors on the same
chip with CMOS devices provides an opportunity for improved
performance.  CMOS circuits retain their low power advantage, while
bipolar devices provide increased drive capability.  To be
successful, a BIFET logic circuit must not dissipate any static
power, and it must generate the full rail-to-rail output voltage
swing that CMOS does. Furthermore, the circuit must not be
significantly more complex than CMOS.  The circuits described herein
accomplish these purposes.

      The inverter circuit shown in Fig. 1 demonstrates the essential
features of the disclosed circuit.  Note that no DC current is drawn
from the logic signal source because the inputs of the circuit are
FET devices.  The bipolar output stage provides better drive than a
CMOS stage could.  Rise and fall times, particularly for large
capacitive loads, are therefore faster than a typical CMOS circuit.

      It is important to keep each of the bipolar devices out of the
saturation region to avoid large delays.  It is impossible for
transistor Q5 to saturate because the base voltage cannot be made
higher than the collector. Transistor Q6 is prevented from saturating
by the feedback path provided by transistor Q3.  As long as the
output voltage is greater than the base-emitter drop of Q6,
transistor Q6 will have base current that generates collector current
which continues to discharge the load capacitance.  As the falling
output voltage approaches the base-emitter voltage of Q6 the feedback
current passing through Q3 will diminish, eventually going to zero
and cutting off Q6.  This action keeps Q6 out of saturation while
dissipating zero static power.  (This feedback circuit has been used
before and is not novel.)

      The primary contribution of this disclosure is the addition of
resistor R1.  Without resistor R1 the output up level would stabilize
at one VBE drop below VDD, and the down level would settle at one VBE
drop above ground.  These are marginal output levels which tend to
cause leakage currents in the succeeding stages.  This can be a
significant problem in VLSI circuits where there are a large number
of circuits.  Noise margin is also degraded accordingly.  Resistor R1
provides a path from the input CMOS inverter stage Q1 and Q2 to the
output terminal which is capable of charging the load capacitance
either to VDD or ground, whichever is appropriate.  This final
improvement in signal swing is not nearly as fast as the initial
transient generated by the bipolar transistors, but it does
eventually provide the desired static levels.  Static power is zero
because both of the bipolar transistors are cut off and the load is
capacitive.

      In Fig. 2, the resistor can be replaced with a parallel
combination...