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Browse Prior Art Database

Interrupt Service Allocation Technique for the Micro Channel Bus

IP.com Disclosure Number: IPCOM000100868D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 7 page(s) / 267K

Publishing Venue

IBM

Related People

Bonevento, FM: AUTHOR [+5]

Abstract

This article describes a technique and hardware implementation in a processor system that allows multiple cards to share a single MICRO CHANNEL* interrupt with minimal software overhead.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Interrupt Service Allocation Technique for the Micro Channel Bus

       This article describes a technique and hardware
implementation in a processor system that allows multiple cards to
share a single MICRO CHANNEL* interrupt with minimal software
overhead.

      Typically, the MICRO CHANNEL bus supports interrupt sharing be
tween devices.  When an interrupt becomes active, the system
determines which interrupt level is active and passes control to the
appropriate interrupt handler for that level. Within the interrupt
handler, the software does a sequential polling of each card on that
level to determine which card presented the interrupt.

      The technique described herein allows software to identify an
interrupting device on a shared MICRO CHANNEL interrupt level without
polling every card that shares the level.  Programmable option
selection (POS) is used to assign an interrupt identification (ID) to
each card sharing a given interrupt level.  When an interrupt is
generated by one or more cards on that level, the interrupt service
routine can read a single interrupt status port to determine which
card or cards have presented interrupts on that level.  Interrupting
cards will pull the channel data bus bit low that corresponds to
their assigned ID value.

      Features of the MICRO CHANNEL bus, such as POS and level
sensitive interrupts, allow for an efficient mechanism for sharing a
single interrupt level by multiple cards of a similar type, such as
parallel printer interface cards or serial interface cards.  A single
I/O port can be used to identify which of several cards has requested
interrupt service on a shared interrupt level.  This port is called
the direct interrupt vector port (DIVP).

      POS can be used to assign each card a unique interrupt ID
value.  When a card generates an interrupt, the interrupt service
routine for that level can read the DIVP on the MICRO CHANNEL for the
level to determine which card or cards have presented interrupts.  An
interrupting card will pull the appropriate data bus bit low (e.g.,
card 0 will pull bit 0 low, card 3 will pull bit 3 low).  This
technique allows 8 cards (8-bit interrupt status port) or 16 cards
(16-bit interrupt status port) to share a single interrupt level.
Identifying the interrupting card or function is done by a single I/O
read instead of by polling each card sharing the interrupt level.

      This disclosure also deals with isolating an interrupt that has
been presented by a card that has multiple devices that are capable
of interrupting.  This technique uses a register on the card that is
assignable by POS.  This register is referred to as the direct
Interrupt ID Register. After the software has determined which card
has interrupted, the service routine will read the Device Interrupt
Identification Port (DIIP).  By reading the DIIP, the service routine
can determine, by the bits assigned at POS, which device has
presented an inter...