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Cascode Logic Buffered Circuit With Regulated Push-Pull

IP.com Disclosure Number: IPCOM000100873D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Beranger, H: AUTHOR [+3]

Abstract

The article relates to a means of implementing an NPN push-pull driver that drastically improves the overall logic gate delay and also reduces the average power since the steady-state dissipated power is very small compared to a traditionnal emitter-follower driver circuit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cascode Logic Buffered Circuit With Regulated Push-Pull

       The article relates to a means of implementing an NPN
push-pull driver that drastically improves the overall logic gate
delay and also reduces the average power since the steady-state
dissipated power is very small compared to a traditionnal
emitter-follower driver circuit.

      The new circuit also includes a voltage regulator which
provides a means for controlling the output buffer characteristics.
This control will also have the great advantage to provide a buffer
with a narrow performance window (speed and dissipated power). It
also has a secondary beneficial effect, in the sense that it
decouples the power supply noise from the logic signals.

      The proposed logic gate and its output stage buffer are means
for removing a lot of drawbacks associated with usage of the Cascode
Current Switch (CCS) logic family.

      The circuit is built around three different functionnal blocks.
One of these is a well known CCS circuit which is the basis for logic
function implementation.  As shown in Fig. 1, the output buffer stage
comprises an NPN push-pull circuit.  Fig. 1 also clearly shows that
the CCS tree is not fed directly from a VCC rail as is usually the
case. One can see that a specificic regulated voltage (VCP) is used
instead of VCC. The purpose of this feature is to regulate the push-
pull buffer operating point when the VCC power supply and/or the
junction temperature are being shifted.  A description for each of
these blocks is given below.

      CASCODE CURRENT SWITCH Fig. 1 (box B) shows a two-level
single-ended CCS circuit. The major difference over standard CCS
circuits resides in the fact that an on-chip regulator provides an
intermediate voltage VCP which biases the cascode tree.

      One can notice that box B could be replaced by either a
differential CCS or an ECL type of logic circuit.

      PUSH-PULL BUFFER The push-pull buffer (box C) is built with
three distinct elements:
      -  Pull-up command (TPU).
      -  Pull-down command (TB, RB, TPD).
      -  Output clamp (TCL connected to VCL).

      The pull-up transistor TPU operates as an emitter follower. Its
base is directly driven by one of the two cascode collector outputs.
The two nodes OP and IP can be swapped to provide a reverse-phase
buffer.

      The pull-down transition is operated through transistor TPD
connected as a common emitter. The base current is provided by a
voltage drop developed across the resistor RB through transistor TB,
which also acts as an emitter follower.  The base current I(RB)) is
amplified by TPD.  As soon as the output voltage reaches one Vbe
below the clamp voltage reference VCL, transistor TCL starts to drain
the...