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Design Which Allows the Use of Partially Good Data-Cache Chips in a System Configuration

IP.com Disclosure Number: IPCOM000100877D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Montoye, RK: AUTHOR [+2]

Abstract

High-end microprocessor chips can be designed such that the Data-Cache Unit (DCU) logic module can have a partially good array and still be useable in a reduced performance mode if a part of the array fails or, in a lower cost system, if the DCUs are manufactured with array faults which do not effect particular functions of the DCU arrays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Design Which Allows the Use of Partially Good Data-Cache Chips in a System Configuration

       High-end microprocessor chips can be designed such that
the Data-Cache Unit (DCU) logic module can have a partially good
array and still be useable in a reduced performance mode if a part of
the array fails or, in a lower cost system, if the DCUs are
manufactured with array faults which do not effect particular
functions of the DCU arrays.

      An all-good high-end system configuration has a 64kB SRAM
data-cache which is 4-way set associative.  The Fixed Point Unit
(FXU) has been designed such that the data cache directory control
logic can be configured to individually exclude data-cache sets.
With this mechanism, the data caches can have an array bit-line or
cell failure which would otherwise render the DCU scrap from a
manufacturing standpoint.  In applications where a high degree of
system availability is critical, the system could be restarted and
reconfigured not to utilize the failing portion of the DCU arrays.

      Static Random-Access Memory (SRAM) designs have included
redundancy schemes to enhance yield for a significant period of time.
These schemes will be increasingly used to increase the utilization
of chips with small numbers of defects as VLSI circuit densities
continue to grow.  Two popular forms of redundancy are word-line and
bit-line redundancy.  A SRAM consists of three basic items:
   1)  A word-line unit which addresses a physical row of cells.
   2)  A bit-line unit which collects or sends data to the particular
section of the physical row addressed by the word-line.
   3)  A cell which stores the 1 or the 0 at the intersection of the
word-line and bit-line.

      The failure frequencies of the SRAM in decreasing order are:
cell,...