Browse Prior Art Database

56KBPS Rate Adapter for an Integrated Service Digital Network Primary Card

IP.com Disclosure Number: IPCOM000100879D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 105K

Publishing Venue

IBM

Related People

Andrade, RJ: AUTHOR [+2]

Abstract

In an integrated service digital network (ISDN) environment data flows on B-channels at a 64kbps transport rate through 64kbps clear channel facilities. When ISDN data must be routed through a restricted 56kbps facility, rate adaption is needed. In many communication systems a signal processor, RAM and software are used to perform the rate adap tion. This requires large amounts of hardware and software. The rate adapter disclosed herein uses a specialized hardware scheme, where a counter, timing logic and bit buffers are used to perform the rate adaption.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

56KBPS Rate Adapter for an Integrated Service Digital Network Primary Card

       In an integrated service digital network (ISDN)
environment data flows on B-channels at a 64kbps transport rate
through 64kbps clear channel facilities.  When ISDN data must be
routed through a restricted 56kbps facility, rate adaption is needed.
In many communication systems a signal processor, RAM and software
are used to perform the rate adap tion.  This requires large amounts
of hardware and software. The rate adapter disclosed herein uses a
specialized hardware scheme, where a counter, timing logic and bit
buffers are used to perform the rate adaption.

      The hardware scheme of this disclosure consists of two main
component parts as follows:
1.   A 56-bit counter responsible for counting the amount of incoming
8-bit bytes and timing the required amount of shift clocks.  The
counter enables the swapping of two 56-bit serial shift registers on
reaching the count of 56.  In addition, the counter also enables
timing logic on board to generate 7- and 8-bit shifts to process both
incoming data (8-bits) and outgoing data (7-bits).
2.   Two 56-bit serial registers (buffers), one being loaded with
incoming data, and the other previously loaded and now being rate
adapted, are swapped every 56 incoming bits.  There is also
additional logic associated with the buffers that gates the clocks
and switches the buffers to maintain the system synchronous.

      The drawing is a block diagram of the logic required for the
56kbps rate adaption.  It is one half of the rate adapter (i.e., the
transmit function) and the following key functions:
A.   A parallel/serial holding register accessible by the card's
firmware which reads in the incoming 8-bit byte to be adapted from an
external input buffer.
B.   Time logic function that performs the switching between the full
and empty 56-bit registers and gates all the necessary clocks.
C.   A 56-bit counter to control the timing and swapping of
registers.
D.   A serial/parallel holding register accessible by the card
firmware that maps in the stored 56-bit incoming stream into 7-bit
bytes and writes...