Browse Prior Art Database

Stop L2 Hold Function

IP.com Disclosure Number: IPCOM000100883D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR [+4]

Abstract

Disclosed is a method of stopping all latches on a VLSI chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Stop L2 Hold Function

       Disclosed is a method of stopping all latches on a VLSI
chip.

      Some current chips gate the L1 clock to all latches with a
signal called Stop_L1.  This signal is generated by self-test logic
using L2 latches and some combinational logic.  The signal has one
half cycle to propagate across the chip.
      The half-cycle time is very hard to meet.

      This invention converts the Stop_L1 to a Stop_L2.  It also
provides a special circuit for latches with L1 outputs. The designs
disclosed provide the exact same function as today's Stop_L1 so:
      -    no self test logic changes are required, and
      -    old (Stop_L1) chips can be mixed with new
           (Stop_L2) chips in a system.

      Since this hold signal is now a full cycle, it could be used
functionally.  Implementation details such as these are not a part of
this disclosure.

      Figs. 1 and 2 show the logical function of Stop_L1 and Stop_L2.
Fig. 3 shows stopping a latch and then restarting it to scan it out.

      Note that the data out of the latch is exactly the same in both
cases.  This is always true for latches with only L2 outputs.

      Figs. 4 and 5 show the implementation for latches with L1
outputs.  Data feedback through the scan path is used so that the L1
latch freezes in the same state as it does in the Stop_L1
implementation.