Browse Prior Art Database

Deterministic Array Self-Test

IP.com Disclosure Number: IPCOM000100885D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Peterson, MJ: AUTHOR [+2]

Abstract

Disclosed is a method of self-testing embedded arrays (RAMs). This uses the self-test control (COP) already on the chip to provide a deterministic array test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Deterministic Array Self-Test

       Disclosed is a method of self-testing embedded arrays
(RAMs).  This uses the self-test control (COP) already on the chip to
provide a deterministic array test.

      Figure 1 shows the logic required for a typical embedded array
today.  Read and write addresses are provided directly from the COP
during array test.  Data in and data out can have some logic in the
path to and from the array.

      Data in is pseudo-random during the present array test. This
data must be deterministic to meet manufacturing requirements.

      Figure 2 shows a typical Scan String configuration for today's
chips.  The data-in and data-out registers can be located anywhere in
any Scan String.

      The Scan Strings need to be reorganized so that deterministic
values can be loaded into the data-input registers.  Constant values
also need to be loaded into all latches affecting (multiplexer) MUX
selection for data input and output.
 The logical view of this scan configuration is shown in Figure 3.

      Also shown is the MISR getting just the value from the
data-output register.  The LFSR bits are used to gate these values
into the MISR.
 These changes are required to identify failure arrays.

      Figure 4 pulls the entire picture together, four new latch bits
are added to the COP to select the "MODE" of operation of the array
self-test.  Gates and multiplexers are added to the chip Scan
Strings.

      If these l...