Browse Prior Art Database

Technique for Early Detection of Errors in Vlsi Logic Design

IP.com Disclosure Number: IPCOM000100889D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 140K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR [+2]

Abstract

Disclosed is an effective technique for early detection of logic errors in VLSI logic design. This technique reduces CPU time and engineer time required to detect certain definable errors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Technique for Early Detection of Errors in Vlsi Logic Design

       Disclosed is an effective technique for early detection
of logic errors in VLSI logic design.  This technique reduces CPU
time and engineer time required to detect certain definable errors.

      VLSI logic designs tend to have many logic errors, most of
which can be detected by building software simulation models and
running test patterns against these models and comparing results with
expected results.  Simulation runs require expensive CPU and engineer
time to analyze results.

      This technique accomplishes two objectives:
         1.  Early detection of hard-to-find logic errors.
         2.  Reduce development, CPU and engineer time in
             detecting errors.

      An example of a "hard-to-find logic error" could be a case when
an error occurs but is not detectable (or observable) during
simulation because it requires the parallel occurrence or subsequent
occurrence of some other condition in the logic design.  If the
parallel or subsequent condition does not occur, then the error is
not observable in a particular test pattern.  If the subsequent
condition does not occur soon enough, then it may be possible for the
logic to get into a state where the subsequent condition no longer
causes an observable error.  Any of these cases mask or hide errors,
and may require extensive amounts of simulation to detect errors.
Another case where a subsequent condition causes problems is when the
subsequent condition occurs several hundreds or thousands of clock
cycles after the primary error.  In this case, an engineer is
required to trace the error condition back from the subsequent
condition over several hundred cycles until the primary error is
found. These cases require significant engineering time to debug as
well as extra CPU time to simulate the extra clock cycles required
before the subsequent condition occurs.  Both of the cases above
extend development time and waste CPU time. The second case requires
significant engineering time to debug the error.  The following
technique can help minimize lost time due to the above problems.

      This technique has three steps:
           1.   Define Primary Error.  This step requires defining
the error in a manner such that an algorithm can be constructed to
detect the error.  This can be a set of conditions that are true when
the primary error occurs.
           2.   Implement error detection algorithm from step one
into the simulation model.  This step can be implemented in two
different methods.  The first method is to implement the algorithm
into the simulation control program.  This is possible only if the
program interrogates the simulation model every cycle.  The
disadvantage of this method is that it is usually slow since the
control program is usually not executed as fast as the logic model.
The second method is to implement...