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Diagnostic Interrupt Force Mechanism for a Level Sensitive Interrupt Structure

IP.com Disclosure Number: IPCOM000100895D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 160K

Publishing Venue

IBM

Related People

Riley, MW: AUTHOR

Abstract

A mechanism is described that allows diagnostic software to test the interrupt structure of a microprocessor system that consists of a processor subsystem, an I/O backplane and I/O feature cards.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Diagnostic Interrupt Force Mechanism for a Level Sensitive Interrupt Structure

       A mechanism is described that allows diagnostic software
to test the interrupt structure of a microprocessor system that
consists of a processor subsystem, an I/O backplane and I/O feature
cards.

      Typical microprocessor systems use an interrupt mechanism to
allow feature cards to report information to the main processor unit.
The interrupt mechanism normally resides in an integrated circuit
that provides the necessary handshake signals.  Fig. 1 shows a block
diagram of a microprocessor system that uses an interrupt mechanism.

      One of the problems of an interrupt mechanism is determining
when the base interrupt mechanism is functioning properly.  For
example, in the configuration shown in Fig. 1, there is no way to
test the interrupt logic without actually programming the feature
card to activate the interrupt line(s) that it uses.  Also, the
interrupt mechanism for the system shown in Fig. 1 lacks a means of
determining which of the three system components failed.

      There are three locations that the interrupt mechanism of Fig.
1 can fail:  1) the processor subsystem, 2) the I/O backplane, and 3)
the I/O feature card.

      The processor subsystem contains the logic to detect when an
interrupt has been asserted.  This logic contains some mechanism to
allow the processor to read the state of the interrupt signals.  A
failure can be incurred by the processor subsystem when the receiver
logic fails.

      The I/O backplane may contain logic to buffer/redrive the
signals to the processor subsystem.  An interrupt failure could also
occur with the backplane logic.

      Finally, the interrupt driver on the feature card could fail.

      In order to test the interrupt mechanism, a diagnostic
mechanism is needed.  To test the interrupts, the following functions
are needed:
      1)   A means of forcing the interrupts to a logic "0".
      2)   A means of forcing the interrupts to a logic "1".
      3)   A means of reading the interrupt values.

      For a system containing 16 interrupt lines, the interrupt force
mechanism would require a minimum of 16 signals to force the
interrupt to a certain value and 16 lines to read the value of the
interrupt after it has been forced to a particular logic value.  For
a gate array implementation, 32 pins could be quite expensive for a
diagnostic function of this nature.

      An interrupt force mechanism can be created by using three pins
on a gate array and two 74F244 TTL modules.  The three pins provide a
means of enabling the diagnostic interrupt mechanism, a means to
force the interrupts, and a means to monitor the interrupts.  Fig. 3
shows how the gate array would be connected to the TTL logic and the
interrupts.

      The Interrupt Enable pin is used to enable the 74F244 output
drivers.  This effectively enables or disabl...