Browse Prior Art Database

Self-Test Method of Data Streaming of I/O Interface

IP.com Disclosure Number: IPCOM000100896D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 108K

Publishing Venue

IBM

Related People

Kumaki, A: AUTHOR [+4]

Abstract

Disclosed is a test method for the Data Streaming function of a control unit (CU) which is attached to a host computer I/O interface. This method has the following characteristics: - Simulation of channel responses by own signals using unique tag wrap plug 1. Simulation of 'data out' by 'data in' 2. Simulation of 'service out' by 'service in' 3. Simulation of 'operational out' by 'operational in' - Data transfer at real rate (3 megabytes per second or 4.5 megabytes per second) - Self-test by CU resident microcode

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Self-Test Method of Data Streaming of I/O Interface

       Disclosed is a test method for the Data Streaming
function of a control unit (CU) which is attached to a host computer
I/O interface.  This method has the following characteristics:
 -  Simulation of channel responses by own signals using unique tag
wrap plug
1.  Simulation of 'data out' by 'data in'
2.  Simulation of 'service out' by 'service in'
3.  Simulation of 'operational out' by 'operational in'
 -  Data transfer at real rate (3 megabytes per second or 4.5
megabytes per second)
      - Self-test by CU resident microcode

      Figure 1 shows the configuration of a Channel Subsystem (CSS)
in which this method is implemented.  It consists of the following
parts:
      - Channel Adapter (CA)
      - Buffer Memory
      - Channel Interface Driver/Receiver
      - Tag/Bus Multiplexer
      - Tag/Bus Control Registers

      CA performs tag/bus sequences according to inbound tags and
buses, and stores data from the channel to Buffer Memory or sends
data to the channel from Buffer Memory.  The multiplexer switches
signal/data paths from CA to driver/receiver or MPU-accessible
registers.  Micro code can simulate the channel by controlling tags
and buses through Tag/Bus Control Registers and a multiplexer, so an
internal self-test of DC-Interlock sequence can be done by this
configuration.

      The tag wrap plug for this method is designed as shown in
Figure 2.

      Initial Selection Sequence (ISS) The diagnostic microcode sets
the Tag/Bus multiplexer to connec...