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Method to Access Individual Embedded Arrays Via Tester Or External Support Processor in a Way Compatible With Built-In Self-Test

IP.com Disclosure Number: IPCOM000100919D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+3]

Abstract

This article describes a way to read and write individual embedded arrays without disturbing the contents of the other arrays. It accomplishes this with minimal additional logic if the chip supports built-in self-test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method to Access Individual Embedded Arrays Via Tester Or External Support Processor in a Way Compatible With Built-In Self-Test

       This article describes a way to read and write individual
embedded arrays without disturbing the contents of the other arrays.
It accomplishes this with minimal additional logic if the chip
supports built-in self-test.

      A typical built-in self-test circuitry usually tests all the
arrays embedded in a chip simultaneously.  All the arrays are put in
the write or read mode and a common address counter is used to step
through the address space. A typical built-in array self-test
sequence is as follows: Pseudo-random patterns are written into the
arrays, data is read out, data is compressed, and the obtained
signature is compared with the good signature.  There is usually an
on-chip controller that controls the self-test sequence. This will be
referred to as a common on-chip processor (COP).  This controller
usually has a bus (COP bus) that is used to program the COP, a few
basic instructions, an address counter, a signature register, and
compression circuitry to generate the signature.  COP generates a
number of signals and broadcasts them to the rest of the chip to
control the self- test sequence.

      With the addition of minimal circuitry, the built-in self-test
circuitry can be used by an external support processor (ESP) to read
or write the arrays one at a time. The ESP is usually a PC or
workstation-based processor that can stop the processor, read the
state of the machine (contents of the registers, arrays, and memory),
display the state, and modify the state.  This method can also be
used by the manufacturing test equipment (e.g., a test set-up
compatible with level sensitive scan design (LSSD) methodology) to
test the individual arrays one at a time (see the figure).

      The new ...