Browse Prior Art Database

Cop Bus Protocol

IP.com Disclosure Number: IPCOM000100923D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR [+2]

Abstract

This article describes communication with multiple-chip internal test points using LSSD scan chains along with a special Common On-chip Processor for control and communication over a serial-type drop bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cop Bus Protocol

       This article describes communication with multiple-chip
internal test points using LSSD scan chains along with a special
Common On-chip Processor for control and communication over a
serial-type drop bus.

      The Common On-chip Processor (COP) was developed as a mechanism
to allow entry into a chip, for the purpose of testing or sending
data to and from a chip while a larger system was operational.

      The main aspect of the COP protocol that is unique is the
ability to synchronize execution of commands from an external source
to a number of different chips along with transferring data between
specific chips and an external source.

      An external source can be either an External Support Processor
(ESP) or an internal On Card Sequencer (OCS).  The configuration of
the COP bus used for communication between the COPs on the chips and
these external controllers is over a COP BUS.  This bus is comprised
of unidirectional lines at the moment for data referred to as Scan
Out (SO) and Scan In (SI), Scan/shift clock (COP CLOCK), and COP
control/ attention (COP CNTL).  The SO and SI lines may be combined
into one line in the future.

      All data into the COP is over the SI line, data out of the
COP is over the SO line, and clocking comes from the Scan/shift
clock.  The COP control/attention is the actual mechanism for telling
the COP to listen for an address, determine if the address and
operation to the COPs is finished, and to start all the COPs'
operations simultaneously via a broadcast address and operation.

      All the COPs have a unique address and a broadcast address
(defined as "O") that they can respond to. Addresses are hard-wired
internally within the COP or via external sub-address pins.  This
allows individual chips to be communicated with, using a very narrow
bus width (small number of signal lines).

      Figure...