Browse Prior Art Database

High Speed/Low Power Charge Buffered Active Pull Down ECL/NTL Circuits

IP.com Disclosure Number: IPCOM000100932D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

Chuang, CTK: AUTHOR

Abstract

Disclosed is a charge-buffered active-pull-down scheme to improve the power-delay performance and loading sensitivity of ECL/NTL circuits. The operating principle and advantages are described below using the ECL as the example.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed/Low Power Charge Buffered Active Pull Down ECL/NTL Circuits

       Disclosed is a charge-buffered active-pull-down scheme to
improve the power-delay performance and loading sensitivity of
ECL/NTL circuits.  The operating principle and advantages are
described below using the ECL as the example.

      Recently, an AC-coupled active-pull-down scheme was invented to
reduce the power consumption and enhance the speed of ECL circuits
(1).  The scheme utilized a capacitor to couple a transient voltage
pulse to the base of the pull-down NPN transistor (Fig. 1), thus
reducing the DC power consumption in the emitter-follower stage and
improving the pull-down delay owing to the large transient pull-down
current.  However, the use of the capacitor imposes the requirement
of AC-testing of the circuit in product qualification.  Furthermore,
the coupling capacitor represents a loading to the logic (current
switch) stage, and substantial power consumption is still needed in
the current switch to achieve fast switching.

      In the present scheme (Fig. 2), a charge storage diode (3,4) is
used as the coupling device between the common emitter node of the
switching transistors T1 and T2 (Node A) and the base of the
pull-down NPN transistor TD (Node B). Transistors T3 and R3 form the
biasing circuit to establish the standby current in the push-pull
driving stage and also serve to quickly stabilize the potential at
Node B after the switching transient to improve the cycle time.  The
charge storage diode is designed to have a large charge storage time
constant in order to act as a buffer for the large amount of charge
to be transferred between the diode and the pull-down NPN transistor
TD. This charge transfer results in a large dynamic current in either
direction during switching, enabling fast charging/discharging of the
pull-down transistor.

      This charge buffered active-pull-down scheme not only provides
a very strong base drive for TD to improve the pull-down delay and
loading sensitivity, but also improves the power consumption and
speed of the current switch logic stage.  For the case when the input
rises to 'High', the voltage at Node A will follow immediately once
the input crosses the reference voltage (ground in Fig. 2), resulting
in a large dynamic current ICSD to charge u...