Browse Prior Art Database

Byte After Byte Fast DMA Mechanism

IP.com Disclosure Number: IPCOM000100936D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Bardet, G: AUTHOR [+4]

Abstract

In digital communication, the protocol used over most serial links is the HDLC or SDLC (High level or Synchronous Data Link Control). There is the need for serial received data to be stored in parallel in a RAM as whole frames, in order for the microprocessor to interpret and take appropriate action upon completion of reception of those whole frames. This article describes a byte after byte fast DMA (Direct Memory Access) mechanism imbedded in a HDLC or SDLC receiver that allows storing incoming data bytes in a RAM.

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Byte After Byte Fast DMA Mechanism

       In digital communication, the protocol used over most
serial links is the HDLC or SDLC (High level or Synchronous Data Link
Control).  There is the need for serial received data to be stored in
parallel in a RAM as whole frames, in order for the microprocessor to
interpret and take appropriate action upon completion of reception of
those whole frames. This article describes a byte after byte fast DMA
(Direct Memory Access) mechanism imbedded in a HDLC or SDLC receiver
that allows storing incoming data bytes in a RAM.

      Fig. 1 shows the principle of operation.  The system
environment includes a microprocessor with its specific time cycle
and a RAM (not shown).  As the serial data arrives in the
deserializer 3, the bit clock is divided by 8 in counter 1 which thus
provides the whole system with byte timing.  At each byte reception,
a HOLD signal is sent to the microprocessor which is stopped (leaves
address and data busses in high impedance), and replies with a HOLD
ACKNOWLEDGE (HLDA) signal.  At this time, the timing generator 2
delivers all the signals needed for the RAM to be written (address
bus, write and chip select) while data bus is supplied by the
deserializer 3.  An identical process is repeated every byte.
Microprocessor activity is thus held during a very short time (a few
time cycles).  This apparatus allows a very good optimization of the
bus bandwidth of any microprocessor.

      Figs. 2 and 3 ...