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Counter Circuitry for Interfacing the North American Communication Rate Of 1.544 MHZ to 8 KHZ Sampling Frequency

IP.com Disclosure Number: IPCOM000100961D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Andrade, RJ: AUTHOR [+6]

Abstract

A counter circuit is described to interface the North American telecommunication rate of 1.544 MHz to an 8 KHz sampling frequency without discriminating each and every half clock cycle. Additional logic is added to European mode circuitry so as to accommodate the two different operational frequencies. This enables operation to function at the North American communication rate.

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Counter Circuitry for Interfacing the North American Communication Rate Of 1.544 MHZ to 8 KHZ Sampling Frequency

       A counter circuit is described to interface the North
American telecommunication rate of 1.544 MHz to an 8 KHz sampling
frequency without discriminating each and every half clock cycle.
Additional logic is added to European mode circuitry so as to
accommodate the two different operational frequencies.  This enables
operation to function at the North American communication rate.

      For the North American communication mode of operation, the
primary telecommunication rate is 1.544 MHz and the normal sampling
rate for voice is 8 KHz.  The 1.544 MHz is generally derived from a
very stable source and must be used as the master clock for the 8 KHz
sampling rate. The dividing factor for the 1.544 MHz master clock
would be 193, which is an odd number.  This factor requires special
arrangements in the counter design to accommodate the ability to
count half clock cycles.  The concept described herein avoids the
complexity of counting half cycles and allows handling the European
primary rate of 2.048 MHz.

      The design consists of two circuits.  The first circuit is
capable of counting up to 96 or 97 counts, and the second circuit
incorporates a discriminator which determines if a delay on the
transition at the output signal of one-half of a master clock is
needed and applies the delay appropriately.  Delaying half of a
master clock cycle at the output eliminates the need to count every
half cycle of the master clock.  A transition on the out...