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Browse Prior Art Database

Dynamic Integrated Circuit Power Protection

IP.com Disclosure Number: IPCOM000100971D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 138K

Publishing Venue

IBM

Related People

Zalph, WN: AUTHOR

Abstract

A circuit arrangement is described whereby dynamic logic integrated circuits (ICs) are protected from damage in the event power continues to be applied to the circuits and the clock has failed. Also, the circuit assures that the clock is running before voltage is applied to the integrated circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dynamic Integrated Circuit Power Protection

       A circuit arrangement is described whereby dynamic logic
integrated circuits (ICs) are protected from damage in the event
power continues to be applied to the circuits and the clock has
failed.  Also, the circuit assures that the clock is running before
voltage is applied to the integrated circuits.

      A typical dynamic IC logic cell, as shown in Fig. 1,
illustrates that both the precharge and validation devices are
vulnerable to a large current flow, and ultimate device failure, in
the event input clock operation should fail.

      The concept described herein provides the capability of
detecting various types of clock failures, such as a stuck-high
condition, a stuck-low condition, Hi-Z and DC offset.  The disclosed
circuitry guarantees that the clock input will be operational at the
ICs before power is applied to the logic cell, thereby preventing
damage.  In addition to the protection, the circuit provides a time
delay between a power-down in the event of a clock failure and also a
time delay between the clock starting and power-up time.  In the
event of a loss of clock, the circuit removes the damaging power
extremely fast, regardless of the amount of decoupling capacitance
between the IC's power pins.  This assures low power supply noise,
without a turn-off delay penalty.  The circuit retains excellent
high-frequency decoupling and quick power removal if the clock should
fail.

      The dynamic IC power protection circuit disclosed herein, as
shown in Fig. 2, is comprised of four basic sections:  Stuck-low
Detection Section, Stuck-high Detection Section, Clock Driver Failure
Detection Section and a Power Switch Section.

      In the circuit of Fig. 2, all inverters are of the type 74HCT04
and the input clock is assumed to have a 50/50 duty cycle.  If the
incoming clock duty cycle is not within ten percent of the 50/50 duty
cycle, then a 74F74 flip-flop should be used to divide the incoming
clock by two so as to create 50/50 symmetry for the detection circuit
input.

      The Stuck-low Detection Section is such that if the clock is
operating properly, Node 10 will charge high and remain high.
Otherwise, Node 10 will be held to ground by means of pull-down
resistor 11, indicating a stuck-low failure.

      The Stuck-high Detection Section is such that if the clock is
operating properly, Node 20 will be held low.  If the clock gets in a
Stuck-high condition, capacitor 12 will be charged, bringing Node 20
high, indicating a stuck-hig...