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Browse Prior Art Database

Four-Phase Shift Register Providing a Secondary Port Capability to a Memory Array

IP.com Disclosure Number: IPCOM000101012D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Herman, BD: AUTHOR [+2]

Abstract

A serial shift register is described which can be attached to any folded bit line random-access memory (RAM) array to be used as a serializing secondary port. This shift register can read and write to the RAM array.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Four-Phase Shift Register Providing a Secondary Port Capability to a Memory Array

       A serial shift register is described which can be
attached to any folded bit line random-access memory (RAM) array to
be used as a serializing secondary port.  This shift register can
read and write to the RAM array.

      Basic timing to shift data between registers (serial mode) is
shown in Fig. 2 and described in U. S. Patent 4,322,635.

      Referring to Fig. 1, devices T1 through T6 constitute a basic
four-phase dynamic shift register. Devices T9 and T10 form the
interface between the shift register and array 10 via bit line pair
BL and BLN.  Devices T8 and T7 are also used in conjunction with the
transfer of data from RAM array 10 to the shift register.

      To perform a parallel-out transfer from RAM array 10 to the
shift register stage requires that register shifting be halted with
signals frozen such that PH1D is high and PH1, Ph2, and PH2D are low,
as in Fig. 3.  This condition isolates internal nodes N1 and N2 from
adjoining register stages and leaves node N2 connected to node N3.
If bit lines BL and BLN are latched and set, requiring
synchronization of RAM array and secondary port timings, PHT may be
brought high and bit lines BL and BLN will set the states of the
internal nodes N1 and N2 of the shift register stage.  PHT can be
lowered again, and shifting may resume independent of the RAM array.

      To perform a parallel-in transfer from the...