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Method of Providing Metastable-Free Interrupt Asynchronous Computer Interface Operation

IP.com Disclosure Number: IPCOM000101013D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16

Publishing Venue

IBM

Related People

Dhaliwal, D: AUTHOR [+4]

Abstract

A technique is described whereby computer systems which utilize asynchronous interface architecture, such as the Micro Channel*, are provided a method of operating metastability free when interfaced with synchronous interrupt controllers.

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This is the abbreviated version, containing approximately 25% of the total text.

Method of Providing Metastable-Free Interrupt Asynchronous Computer Interface Operation

       A technique is described whereby computer systems which
utilize asynchronous interface architecture, such as the Micro
Channel*, are provided a method of operating metastability free when
interfaced with synchronous interrupt controllers.

      Typically, Micro Channel architecture features level-triggered
interrupts that are generated asynchronously by devices located on
feature cards or on the system's planar board.  Acknowledge signals
from the processor are also driven asynchronously.  Upon receipt of
one or more asynchronous level-triggered interrupt requests (IRQs),
the corresponding interrupt request register (IRR) bits in the
programmable interrupt controller (PIC) are set.  The PIC then forces
its interrupt line (INTR) high.  The INTR is connected to the
processor to indicate that an interrupt is waiting to be serviced.

      When the processor is ready to service an interrupt, it returns
two interrupt acknowledge (INTA) commands to the PIC.  Both INTA
commands are asynchronous signals.  The first INTA instructs the PIC
to set the in-service register (ISR) bit corresponding to the highest
priority IRQ seeking service.  The IRR bit of the interrupt going in
service is cleared for the duration of the INTA sequence and is only
set again if the IRQ is still active.  However, no IRQ of the same or
lower priority may raise the INTR (fully nested mode).  Therefore,
only IRQs of higher priority may be serviced, until an end of
interrupt command clears the ISR bit.

      The priority is determined by the PIC in accordance with its
programmed value.  When the PIC receives the second INTA, it drives
the interrupt vector on the data bus.  Fig. 1 illustrates a typical
interrupt sequence.  If no other interrupt of higher priority is
performing a request, the INTR line goes low at the end of the second
INTA.  Since the PIC may have any practical number of IRQ inputs with
corresponding IRR and ISR bits, the interrupt handling circuitry must
process asynchronous signals error and metastability free.  When
interfaced with the synchronous environment of scan design, or any
other clocked design, special consideration must be taken into
account to handle the asynchronous interface.

      As the PIC receives IRQs and INTAs, it must latch and
synchronize the signals to the system clock.  Since these signals are
asynchronous, metastable levels may be written into the IRR and ISR
if an INTA is issued with respect to the system clock.  In this case,
the set-up and hold time for the register is violated.  The duration
of an IRQ is long enough, such that the true value would be latched
on the next clock.  This holds also true for the INTA input if the
system clock frequency is high enough.  However, a special case
exists that may latch metastable levels into the IRR and ISR.  In
some cases it may set two or more ISR bits s...