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Timing Generator With Designed-In Compensation for Inherent Delays

IP.com Disclosure Number: IPCOM000101017D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Fleurbaaij, JM: AUTHOR

Abstract

This article describes a timing generator circuit which uses programmable delay lines. Programmable delay lines have inherent delays and this timing generator circuit has circuitry to compensate for the inherent delays of these delay lines.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Timing Generator With Designed-In Compensation for Inherent Delays

       This article describes a timing generator circuit which
uses programmable delay lines.  Programmable delay lines have
inherent delays and this timing generator circuit has circuitry to
compensate for the inherent delays of these delay lines.

      The Timing Generator consists of a RAM, an Address Counter and
the Timing Generator circuits.  The Timing RAM is 1K x 12 and is
addressed by a 10-bit counter.

      The address counter is loaded with a start address prior to
starting execution of a timing sequence and is clocked by the 100 MHz
clock (referred to as the cycle clock).  The information read from
the Timing RAM is used by the Timing Generator Circuits to produce
two edges within a cycle, a leading edge and a trailing edge, and so
timed pulses can be generated.  The Timing RAM is 12 bits wide and
the data format is as follows:
  bit  11   - determines if positive or negative active signal
  bits 10-6 - leading edge delay (32 steps max, each step 1 ns)
  bits  5-1 - trailing edge delay (32 steps max, each step 1 ns)
  bit   0    - end of sequence

      Since a timing sequence can contain a number of cycles, it is
necessary to know when the sequence is finished.  This is done with
the "end of sequence" bit, which is programmed in the last cycle of a
sequence.

      The other bits are used to program the two edges per cycle, the
leading edge and the trailing edge.

      If the leading edge delay and the trailing edge delay are both
set to zero (0), the signal for that cycle will be a constant high or
low, depending on bit 11.

      If only the trailing edge delay is set to zero (0), no trailing
edge is generated (so only one edge per cycle). This is useful where
a pulse is required that is longer than the cycle time.

      TIMING GENERATOR CIRCUIT DESCRIPTION The logic for the Timing
Generator is shown in Fig. 1. Also refer to the timing chart in Fig.
2.

      The CYCLE CLOCK is the basic clock pulse for this circuit.  It
is used to latch the 12 data bits from the Timing RAM in the TIMING
RAM DATA LATCH.  Eleven bits of this data will be used to shape the
Timing generator pulse for that particular cycle.  The remaining bit
is used to signal the end of a timing sequence.

      A 3 nsec pulse is generated from the leading edge of the cycle
clock.  This 3 nsec pulse (called the Cycle Pulse) will do 3 things:
 -  Clock bits 11-6, which represent the leading edge delay and the
positive/negative FF state, into the LEADING EDGE DELAY REGISTER.
The output of this register goes to the program input pins of the
LEADING...