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Parity Prediction in Carry Select Adders

IP.com Disclosure Number: IPCOM000101024D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Temple, JL: AUTHOR

Abstract

One way to speed up an adder is to implement pairs of adders whose results are selected by the carry-in signal. This technique reduces the logic path length of the carry signal, but uses considerably more gates than a simple ripple adder. Parity prediction of an adder uses almost as much silicon area as a double adder design so that a carry select adder with parity predict has on the order of 4X the gates of an unchecked ripple adder.

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Parity Prediction in Carry Select Adders

       One way to speed up an adder is to implement pairs of
adders whose results are selected by the carry-in signal.  This
technique reduces the logic path length of the carry signal, but uses
considerably more gates than a simple ripple adder. Parity prediction
of an adder uses almost as much silicon area as a double adder design
so that a carry select adder with parity predict has on the order of
4X the gates of an unchecked ripple adder.

      This method uses the redundancy inherent in a carry select
adder to perform the checking function with low additional overhead.
The key to this is making use of the fact that the results of the
two adders in a carry select adder pair differ by 1.  Because of
this, parity generated for the Carry-in = 1 result can be predicted
from the parity of the Carry-in = 0 result using the Parity Predict
to incrementers circuit described in a previous article [*].
Similarly the Parity of the Carry-in = 0 result can be used to
predict the Carry-in = 1 result by using the circuit described for
decrementers.  This prediction occurs before the data for the section
selected by the carry-in signal. The parity of the result is checked
after selection, and byte parity is then created by merging the
parity of the selection fields if they are less than a byte long.

      Reference
(*)  "Parity Predictions for Incrementers," IBM Technical Disclosure
Bulletin 18, 5, 1456 (October 1975).