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Global Computer Design

IP.com Disclosure Number: IPCOM000101044D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 142K

Publishing Venue

IBM

Related People

Roth, J: AUTHOR

Abstract

Problems in designing, building and operating computers and chips with large numbers of devices include that of developing a Form of Design which guarantees correct operation. First, it must be determinate, not probabilistic; second, the designs must be testable for their failures. Here "global design" is described which is guaranteed to be determinate and testable for arbitrary size; it is a generalization of R-design, which was used in IBM Systems/360 and /370 and in IBM 3081 and 3090 processor complexes.

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Global Computer Design

       Problems in designing, building and operating computers
and chips with large numbers of devices include that of developing a
Form of Design which guarantees correct operation.  First, it must be
determinate, not probabilistic; second, the designs must be testable
for their failures.  Here "global design" is described which is
guaranteed to be determinate and testable for arbitrary size; it is a
generalization of R-design, which was used in IBM Systems/360 and
/370 and in IBM 3081 and 3090 processor complexes.

      First, we review the elementary design, the R-design. REGULAR
design, R-design, consists in an arbitrary acyclic logic design X
together with input- and output-registers R1 and R2 gated
respectively by "timing pulses" t1 and t2, with 0<t2-t1 the "cycle
time" of the design Z, with feedback allowed from R2 to R1: an
R-design is therefore a perfectly general sequential machine; an
R-design is not used, however, for very large designs, because of
possible need for intermediate storage, etc.

      We now describe "global design".  The method of construction
(design) is recursive.  In this design, the ELEMENTS are themselves
R-de- signs, these R-designs may be interconnected arbitrarily,
except no direct feedback is allowed.  The entire Global (GR)-design
has itself input- and output-registers, R1 and R2, appropriately
timed, with feedback allowed from R2 to R1.

      First consider timing for single R-designs, X preceded and
followed by registers R1 and R2, gated respectively by "timing
pulses" t1 and t2.  The difference t2-t1 is determined so that it is
(slightly) larger than the "longest time" through X, from R1 to R2;
an expeditious way to do this is to use the algorithm in the AC
d-algorithm for determining "longest times" to each device.

      In general an algorithm executed on an R-design "loops", that
is, recurses (such as the Newton-Raphson square-root algorithm); in
the R-design construction there is a "completion signal" emanating
from R2 and determining when the computation is complete; this
completion signal e will then gate the contents of R2, possibly to
R1, depending on the design.  Until e=1, meaning "completion", R2's
contents are held and no new inputs are allowed for R1.  The general
form of GR-design GR is an interconnection of R-designs (acyclic),
with input- and output- registers for the GR-design.  Each R-design
has completion signals, as well as the registers for global R-design
itself.  Register R2 has a completion signal which is determined by
the completion signals of all R-designs which directly feed it. This
is partially an asynchronous system, obtaining maximum speed.

      There, of course, may be several GR-designs linked, one feeding
another, forming Augmented GR-designs.

      GLOBAL R-DESIGN TIMING Each R-design in a Global R-design will
have its own completion signal.  If R-design 1 feeds R-design 2, then
a 1's completion si...