Browse Prior Art Database

Built-In Self-Test of Logic in the Presence of Embedded Arrays

IP.com Disclosure Number: IPCOM000101051D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 119K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+4]

Abstract

This article describes a method to self-test the logic and bypass the embedded arrays, all under the control of a central unit integrated on the same chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Built-In Self-Test of Logic in the Presence of Embedded Arrays

       This article describes a method to self-test the logic
and bypass the embedded arrays, all under the control of a central
unit integrated on the same chip.

      A new method for built-in self-test (BIST) of logic circuitry
is described.  Most new logic chips contain arrays, such as register
files, caches and directories, and this method is particularly
tailored for logic chips that contain embedded arrays.  Logic test is
controlled by a central processor (COP) integrated on the chip.  The
COP controls the self-test sequence, generates pseudo-random
test-vectors, and scans them into chip-registers.  After the vectors
are scanned in, the chip runs for one or two system cycles, the logic
outputs are captured in registers, and the chip state is scanned back
into the COP where it is compressed to obtain a signature.  This
procedure is repeated many times, and the final signature is then
compared with a predetermined "good" signature to establish if the
chip is good or bad.  Special techniques are developed to improve the
coverage of logic that feeds arrays or receives its inputs from
arrays.  Both AC and DC logic tests are described.

      Figure 1 shows a simplified block diagram of logic self-test
hardware.  Pseudo-random test-vectors are generated by COP using a
linear- feedback shift-register (LFSR).  During self-test, COP takes
over the control of the scan chains required by level-sensitive
scan-design (LSSD); the COP drives the scan control inputs of the
registers and can force them in scan-mode when necessary.
Accordingly, random patterns of ones and zeros from LFSR are scanned
into the chip registers under the control of COP.  Once a test-vector
is scanned into the registers, COP lets the chip run for one or two
"functional-like" cycles.  During these cycles, the pseudo-random
state scanned in the chip stimulates the logic and the result is
captured by the registers.  Next, the new chip state is scanned back
into the COP and compressed by a multiple- input signature register
(MISR).  This is repeated many times to ensure a high fault-coverage.
The final value of MISR is the signature.

      As shown in the block diagram in Figure 1, many logic chips
contain arrays embedded in combinational logic. Because one cannot
scan test-vectors indirectly in an array, a scheme must be provided
to prevent the arrays from injecting indeterminate or unrepeatable
states into combinational logic during test.  A good way to achieve
this is to force the arrays in write-through mode during logic
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