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Built-In Self-Test of Arrays Embedded in Logic Chips

IP.com Disclosure Number: IPCOM000101053D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 144K

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Bakoglu, HB: AUTHOR [+5]


This article describes a method to simultaneously self-test all the arrays on a chip using a central control unit integrated on the chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Built-In Self-Test of Arrays Embedded in Logic Chips

       This article describes a method to simultaneously
self-test all the arrays on a chip using a central control unit
integrated on the chip.

      A new method for built-in self-test (BIST) of arrays embedded
in logic chips is described.  As the integration density improves,
arrays (register files, caches and directories) are becoming very
common in VLSI logic chips. In this new method, array test is
controlled by a central processor (COP) integrated on the chip.  The
COP controls the self-test sequence, generates pseudo-random test
vectors, scans them into chip-registers, and provides the
select-lines that establish a one-to-one correspondence between array
input/output and chip-registers ters.  The COP also drives array
read/write lines during self-test, scans the captured array outputs,
and compresses them to obtain a signature.  The signature is then
compared with a predetermined "good" signature to identify chips with
faulty arrays.  Testing of arrays at functional speed (AC test) is
also described.

      Figure 1 shows a simplified block diagram of array self-test
hardware.  Pseudo-random test-vectors are generated by COP using a
linear- feedback shift-register (LFSR).  During self-test, COP also
drives the scan control inputs of the registers and can force them in
scan-mode when necessary.  Accordingly, random pit patterns of ones
and zeros from LFSR are scanned into the chip registers under the
control of COP.  During self-test, COP also provides an array address
generated by a counter, and read/write control signals.  Once a test
vector is scanned into the chip registers, COP activates the array
write signal, and the scanned bits are written into the arrays.  This
sequence is repeated multiple times as the address counter is
incremented.  Because the same counter is used for testing all the
arrays simultaneously, the counter should be big enough to cover the
address space of the largest array on the chip.  Small arrays get
written in over and over.  After all the array locations are
initialized with pseudo-random values, read sequence starts.  Array
read is performed similar to array write, but instead of loading the
output of the LFSR into the array, this time array outputs are
captured in registers, scanned into the COP, and compressed by a
multiple input signature register (MISR).

      In most designs, arrays are not necessarily bound by registers,
and functional, as well as self-test address and control, signals
must be fed to arrays.  Control signals from the COP are used to
establish a one-to-one correspondence between the array data
input/output and chip registers during self-test.  In addition, the
COP address counter and read/write control for self-test are
multiplexed with functional signals.  A typical arra...