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Browse Prior Art Database

Cell Design for Multiple Logic Circuit Families

IP.com Disclosure Number: IPCOM000101060D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Masci, F: AUTHOR [+3]

Abstract

Today's VLSI logic cell size is determined by global wiring, that is, the free and clear wiring tracks required to wire the chip. In addition, a logic chip is designed to support a logic cell for two or three families, for example, ECL, differential logic, and embedded arrays. While this flexibility is a must, an optimum cell performance is also required especially for ECL circuits. Generally, a cell design and layout is a compromise between these requirements. This article shows how to achieve both flexibility and optimum performance at the same time.

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This is the abbreviated version, containing approximately 79% of the total text.

Cell Design for Multiple Logic Circuit Families

       Today's VLSI logic cell size is determined by global
wiring, that is, the free and clear wiring tracks required to wire
the chip.  In addition, a logic chip is designed to support a logic
cell for two or three families, for example, ECL, differential logic,
and embedded arrays.  While this flexibility is a must, an optimum
cell performance is also required especially for ECL circuits.
Generally, a cell design and layout is a compromise between these
requirements.  This article shows how to achieve both flexibility and
optimum performance at the same time.

      These objectives were achieved by using polysilicon silicide
(polywire) as a wiring underpass, as shown in the figure by the cross
hatched areas.  The figure shows the polywire being used in the test
portion of a differential logic circuit.  Polywire has slightly
higher resistance and capacitance per unit length, as compared to the
first or upper level metal wiring, but will not affect performance in
this case.  The utilization of polywire allows the wiring of all
circuit families without blocking free and clear global wiring tracks
on either the second or upper levels of metal. Using the same master
slice as shown in the figure, a high performance circuit (ECL) may be
wired from half a cell where the polywire is not used.  The circuit
layout will be optimum for performance, because minimum node wiring
capacitance and small devices with minimum p...