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Dual-Port Bipolar Memory Cell With Soft Error Rate Immunity

IP.com Disclosure Number: IPCOM000101062D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+4]

Abstract

A bipolar memory cell is proposed that is Soft Error Rate (SER) immune. In addition, the cell meets the requirements of performance, density, yield, and multiport applications.

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Dual-Port Bipolar Memory Cell With Soft Error Rate Immunity

       A bipolar memory cell is proposed that is Soft Error Rate
(SER) immune.  In addition, the cell meets the requirements of
performance, density, yield, and multiport applications.

      Fig. 1 illustrates a bipolar memory cell consisting of
complementary PNP and NPN transistors T1, T2, and T3, T4,
respectively, which form the basis of the latch function. Note that
these devices are operating in the inverse mode. Because the
collectors are now connected to the power supply nodes WL, DL, the
critical area susceptible to alpha particle penetration is greatly
reduced.  Since the major portion of the collector capacitance has
been removed from the switching nodes, a faster write time will be
achieved with comparable read performance.  In addition there are
four lateral NPN transistors T5, T6, T7, T8 which provide access for
reading and writing the cell.  Fig. 2 illustrates the lateral NPN
structure which is easily integrated into the cell (Fig. 3) for an
efficient reduction in cell area over previous multiport bipolar cell
designs.