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Three-Dimensional, Six-Device, CMOS SRAM Cell Structure

IP.com Disclosure Number: IPCOM000101071D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 109K

Publishing Venue

IBM

Related People

Beilstein, KE: AUTHOR [+3]

Abstract

A conventional complementary metal oxide silicon (CMOS) static random-access memory (SRAM) cell circuit is constructed by first etching a P- silicon substrate to form rectangular mesas. N-type transistors and P-type transistors are formed using alternate mesas. A pair of N-type transistors having vertical gate conductors is formed on either side of a mesa while P-type transistors are formed having gate conductors horizontally disposed over a mesa. A layout comprised of four N-type and two P-type transistors and wiring to form the conventional circuit is described.

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Three-Dimensional, Six-Device, CMOS SRAM Cell Structure

       A conventional complementary metal oxide silicon (CMOS)
static random-access memory (SRAM) cell circuit is constructed by
first etching a P- silicon substrate to form rectangular mesas.
N-type transistors and P-type transistors are formed using alternate
mesas.  A pair of N-type transistors having vertical gate conductors
is formed on either side of a mesa while P-type transistors are
formed having gate conductors horizontally disposed over a mesa.  A
layout comprised of four N-type and two P-type transistors and wiring
to form the conventional circuit is described.

      Referring to Fig. 1, the standard SRAM cell circuit is
comprised of bit line BL2 connecting to N-type transistor T2 at 10
and complement bit line BL1 connecting to N-type transistor T4 at 12.
Word line WL connects to the gate conductor of transistor T2 at 14
and also the gate conductor of transistor T4 at 16.  High supply
voltage VDD is connected in common to N-wells and sources of P-type
transistors T5 and T6 at 18.  Ground potential is connected in common
to drains of N-type transistors T1 and T3 at 20. An internal node 22
of the latch is formed by interconnection of points A, B, and C.
Node 24 is formed by interconnection of points X, Y, and Z.  These
connection points are identified in Fig.  2.

      Fig. 2 shows a series of mesas, e.g., 26, 28, and 30, which
remain after etching P- substrate 31, shown in Fig. 3. Mesas 26 and
30 are used for construction of N-type devices such as shown in more
detail in Fig. 3, a cross-section of mesa 26.  Mesa 28 is used for
construction of P-type devices such as shown in more detail in Fig.
4.

      Referring to Fig. 3, the gate G1 of transistor T1 is comprised
of gate insulator 32 and gate conductor 34 disposed vertically along
the right sidewall of the mesa. Diffusion 36 is the drain of
transistor T1.  Diffusion 38 is the common source for transistors T1
and T2, points B and A of node 22 in Fig. 1.  Transistor T2 has
its gate G2 and drain diffusion on the left side of the mesa.
Insulating layer 40 covers gate conductors.  Conductor 42 provides
ground wiring Gnd to the drain of transistor T1.  Conductor 44
becomes bit line BL2 connecting to underlying drain...