Browse Prior Art Database

Power Decoupling Capacitances in CMOS Structures

IP.com Disclosure Number: IPCOM000101075D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Miersch, EF: AUTHOR [+2]

Abstract

Integrated power decoupling capacitances are used to reduce the noise induced by the power supply line inductances during the simultaneous charging and discharging of capacitive loads of internal and external devices of integrated CMOS structures.

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Power Decoupling Capacitances in CMOS Structures

       Integrated power decoupling capacitances are used to
reduce the noise induced by the power supply line inductances during
the simultaneous charging and discharging of capacitive loads of
internal and external devices of integrated CMOS structures.

      It is desirable to have high capacitances in order to avoid
noise problems.

      The figure shows the structural realization of such a high
capacitance and is a partial view of a cross-section of a
semiconductor chip on which CMOS structures with P and N channel
devices (not shown) are integrated.  A P- epitaxial layer 1 with a
buried P+ layer 2 is deposited on an N+ substrate 3.  The N channel
devices are realized in P- layer 1, whereas the P channel devices are
realized in N- wells 4 diffused into P- epitaxial layer 1.  At points
provided for forming these capacitances, P- epitaxial layer 1 with
buried P+ layers 2 is periodically interrupted by N- wells 4.  N-
wells 4 contact N+ substrate 3 in the interrupted regions of buried
P+ layer 2, so that the capacitance between N- well 4 and P-
epitaxial layer 1 is drastically increased and defined by highly
doped buried P+ layer 2 and N+ substrate 3.