Browse Prior Art Database

Pipability Indicator

IP.com Disclosure Number: IPCOM000101078D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Rechtschaffen, RN: AUTHOR

Abstract

Parallel Instruction Processors (PIPs) (multiple sequence processors) have the property that a prior segmentation of the code has been identified and such predefined segments are processed in parallel by different processors (main and auxiliary) so that the overall execution of the code is reduced. In a processor with limited resources, the use of the PIP paradigm for improved execution has certain advantages with regard to the overlap of delay in the different processors, and the earlier detection of a Branch Wrong Guess, but it has a deficit with regard to the resources allotted to processors whose results must be aborted because of a set/use inconsistency.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pipability Indicator

       Parallel Instruction Processors (PIPs) (multiple sequence
processors) have the property that a prior segmentation of the code
has been identified and such predefined segments are processed in
parallel by different processors (main and auxiliary) so that the
overall execution of the code is reduced.  In a processor with
limited resources, the use of the PIP paradigm for improved execution
has certain advantages with regard to the overlap of delay in the
different processors, and the earlier detection of a Branch Wrong
Guess, but it has a deficit with regard to the resources allotted to
processors whose results must be aborted because of a set/use
inconsistency.

      A set/use inconsistency is monitored during the PIP CYCLE so as
to certify the RUBRIC OF SERIAL CORRECTNESS. This RUBRIC asserts that
all processor designs must have the same execution results as a
serial processor which executes each instruction on consecutive
cycles and performs all required operations in zero time.

      An extension of the monitoring operations can determine, at the
time of a BRANCH WRONG GUESS, that the two code segments linked by
the newly detected branch are PIPABLE. The algorithm for the
extension is to monitor each segment both as a caller based on
executed instructions and as a callee based on decoded instructions.
When a BRANCH WRONG GUESS is detected, and a new taken branch is
identified, the caller's use of registers, based on execution up to
the i...