Browse Prior Art Database

Mid-Level Current Generator Circuit

IP.com Disclosure Number: IPCOM000101087D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 93K

Publishing Venue

IBM

Related People

Sunaga, T: AUTHOR

Abstract

A simple circuit configuration to generate a mid-level between two different DC currents is disclosed. This circuit can be used to provide a reference level to a current sense amplifier of a multi-valued read-only memory (ROM).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mid-Level Current Generator Circuit

       A simple circuit configuration to generate a mid-level
between two different DC currents is disclosed.  This circuit can be
used to provide a reference level to a current sense amplifier of a
multi-valued read-only memory (ROM).

      In semiconductor memories, it is a well-known method to use a
dummy cell as a reference to detect stored information.  For example,
dynamic random access memories use dummy cells which have half of the
memory cell capacitance and provide a reference voltage level
intermediate between stored "1" and "0".  In conventional two-valued
ROMs which store one bit per cell, two series-connected transistors
are used for the dummy cell to provide a half of a single cell
current.  However, in N-valued ROMs which store two or more bits per
cell or one of N values per cell (N>2), the memory cells generate N
signal levels.  Therefore, to detect the N signal levels, N-1
reference levels are required for N-1 sense amplifiers. Each of the
reference levels is set to a mid-level between two adjacent values.
It is, however, very difficult to precisely generate reference levels
for such multi-valued ROMs by geometrical variations of transistors.

      The present disclosure provides a circuit configuration for
generating mid-level reference currents for the N-valued ROM.  For
simplicity, Fig. 1 shows a memory circuit in which the present scheme
is applied to a two-valued ROM.  N-MOSFET memory cells are
personalized by varying threshold voltages using ion implantation.
Threshold voltages of the cells are either VT1 or VT2, where we
assume VT2 is higher than VT1.  Then, at the same gate to source
voltage, a cell with VT1 has a higher drain current than a cell with
VT2.  TN3 is an N-MOSFET cell in the ROM.  Its thresh...