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Browse Prior Art Database

DRAM With Multiple RAS Inputs

IP.com Disclosure Number: IPCOM000101099D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Ohsaki, K: AUTHOR [+3]

Abstract

Disclosed is a DRAM (Dynamic Random-Access Memory) in which memory blocks or arrays are selected by multiple RAS (Row Address Strobe) inputs. The memory blocks share some of the memory circuits and the memory allows large skews in the RAS inputs when a plurality of RAS inputs are activated concurrently.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 77% of the total text.

DRAM With Multiple RAS Inputs

       Disclosed is a DRAM (Dynamic Random-Access Memory) in
which memory blocks or arrays are selected by multiple RAS (Row
Address Strobe) inputs.  The memory blocks share some of the memory
circuits and the memory allows large skews in the RAS inputs when a
plurality of RAS inputs are activated concurrently.

      Certain DRAMs use multiple RAS inputs to select memory blocks
or arrays.  A plurality of RAS inputs are concurrently activated in
some cases.  For example, all the RAS inputs are activated at a time
in refresh operations. One method to implement the multiple RAS
feature is to use RAS timing chains, one for each of the memory
blocks. However, the method is uneconomical and requires a large chip
area. Another method is to use a single timing chain in which memory
blocks to be selected are determined based on active RAS inputs at
the start of each cycle to trigger the timing chain.  The method is
economical but apt to cause erroneous operations when the RAS inputs
include skews. The disclosed memory is effective to solve such a
problem.

      In the figure, the memory includes four memory blocks 0-3, and
four RAS inputs 0-3 are used to select corresponding ones.  The
memory shares all circuits other than RAS input buffers 0-3 and word
line boost circuits 0-3, such as address buffer and RAS restore
circuits.  The RAS inputs are applied to a NAND circuit to activate
an address buffer circuit.  Thus, the RAS access...