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Refresh Address Counter Test for Dynamic Random-Access Memories

IP.com Disclosure Number: IPCOM000101101D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 105K

Publishing Venue

IBM

Related People

Redman, TM: AUTHOR [+2]

Abstract

Test modes described by JEDEC standards for dynamic random-access memories (DRAMs) are used to reset the refresh access counter (RAC) to an initial state and to activate a signal path to a chip pad to indicate status of the counter in a final state. The RAC test circuits use address path portions of memory chips and do not use memory array cells to test the RAC.

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This is the abbreviated version, containing approximately 52% of the total text.

Refresh Address Counter Test for Dynamic Random-Access Memories

       Test modes described by JEDEC standards for dynamic
random-access memories (DRAMs) are used to reset the refresh access
counter (RAC) to an initial state and to activate a signal path to a
chip pad to indicate status of the counter in a final state.  The RAC
test circuits use address path portions of memory chips and do not
use memory array cells to test the RAC.

      Fig. 1 is a block diagram of the RAC test circuits and a
portion of the address circuits of a memory chip.  RAC 1, for most
applications, is a binary counter having one stage for every row
address supplied to the chip.  Output of RAC 1, lines 14, go to
address buffers 2 which generate address signals on lines 7 that are
used by the memory array circuits and the RAC test mode circuits, RAC
reset 3, RAC test enable 4, and RAC test mode 5.

      RAC reset circuit 3 is an address decoder personalized to
respond to one unique address, the RAC reset test mode address, when
mode set signal 12 is active.  RAC reset line 6 puts RAC 1 into an
initial state.

      RAC test enable circuit 4 is an address decoder personalized to
respond to one unique address, the RAC test mode enable address, when
mode set signal 12 is active.  RAC test mode enable line 11 activates
RAC test mode circuit 5 which is an address decoder personalized to
respond to one unique address, the address present when RAC 1 is in a
final state.

      To generate a signal on RAC test output line 8, A) test enable
line 11 must be active, B) only a row address is transferred into
test...