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Browse Prior Art Database

Use of LSSD Constraints for Optimized Serial Multiplexing of Registers Content

IP.com Disclosure Number: IPCOM000101104D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 177K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR [+2]

Abstract

This article describes write and read register operations which allow to reduce the required logic circuitry by taking advantage of the LSSD (Level-Sensitive Scan Design) latches.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Use of LSSD Constraints for Optimized Serial Multiplexing of Registers Content

       This article describes write and read register operations
which allow to reduce the required logic circuitry by taking
advantage of the LSSD (Level-Sensitive Scan Design) latches.

      A TDM link structure which allows accommodating 32 users at any
speed up to 64 kbps, with each user having an 8-bit Data slot and an
8-bit Control slot on the link is described in published European
Patent application 232,436. As shown in Fig. 1, the users are
connected to the communication scanner 1 through an active tail gate
(ATG) 2 which performs the multiplexing/demultiplexing of the user
information and line interface couplers (LICs) 3.

      The complete string of 64 slots (Data and Control) related to
the 32 users will be called a frame in the following.

      The control slot carries three different types of information:

      External control information required to handle the line
interfaces the LICs are attached to, like V.24, V.35, X.21, Bell 303,
etc.  This type of information must be exchanged between the scanner
and the ATG in synchronism with the data due to the fact it is used
to validate this data. This requirement implies that the main part of
the control slot is reserved for external control (4 bits out of 8).

      . Service bits which are used to validate the data in case of 8
bits data transfer (global bit) and to ask the scanner a new data
slot following the line clock speed (transmit request bit). This
service information will then require 2 bits in the control slot.

      . Internal control information which mainly relates to two
types of operations:
           Allocation of ATG link offerings: an ATG resource
(register) related to the physical ATG population has to be read and
conversely another resource must be written by the scanner; it will
allow the scanner to assign one or more offerings (i.e. data/control
slot pair) to each user following the type of attachment (physical or
logical multiplexed) and its speed.
           Handling of other ATG internal resources for a given
attachment or for a group of them and related to attachment
specificities (type of external interface, type of cable, etc.) or
diagnostic control (wrap test mode).

      Eight registers of 8 bits are sufficient to support all
necessary internal control information related to each user.

      Due to the fact that the control slot is mainly filled by
external control information and service bits, the information
exchanged with the LIC's register housing internal control must be
multiplexed on one bit (I bit). In order to do so, a delimiter must
be provided and carried in the control slot along with I bit; this
delimiter is a control slot numbering bit (N bit) and allows a modulo
n framing mechanism.

      A simple way to implement this mechanism is to set this bit ON
in one receive/transmit control slot ou...