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Browse Prior Art Database

Clock Timing And Stressing Scheme Using Silicon Delay Blocks

IP.com Disclosure Number: IPCOM000101110D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Singh, B: AUTHOR

Abstract

Disclosed is a scheme to use on-chip silicon delay blocks for clock timing and stressing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Clock Timing And Stressing Scheme Using Silicon Delay Blocks

       Disclosed is a scheme to use on-chip silicon delay blocks
for clock timing and stressing.

      As system cycle times are reducing, maintaining clock signal
integrity and reducing statistical variations in clock signal arrival
times are taking on great importance. By eliminating the use of
discrete delay lines and package wiring for timing clocks, signal
distortion and clock skew can be minimized.

      The figure shows the logic for this scheme.  The delay block 1
represents the minimum delay increment.  Multiplexer 2 and scan
registers 3 select a particular amount of delay. Latches 4 isolate
multiplexer 2 during scanning of scan registers 3.  Once the scan
registers 3 are scanned in with the proper selection code, a single
clock pulse to the latches 4 will transfer the selection code to the
input of multiplexer 2.  This logic scheme will also be repeated on
other clock inputs.  Since all scan registers 3 for all clock inputs
will be on a single scan ring, it is very essential that each clock
input's delay amount be independently controllable.  This is achieved
by interposing latches 4 inbetween the scan registers 3 and the
multiplexer 2.  Logic 5 produces a single pulse of latch clock when
the CNTL signal is brought active for one cycle.

      Clock path delay can be measured, and the disclosed scheme
used, for timing adjustments in hardware without going through the
time-consum...