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Common On-Chip Processor for Built-In Self-Test Debug Field Support

IP.com Disclosure Number: IPCOM000101126D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 7 page(s) / 225K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+6]

Abstract

This article describes a sophisticated piece of hardware called COP (Common On-chip Processor), integrated in one physical macro and responsible for providing the necessary support and control logic needed to achieve built-in self-tests, power on reset, debug and field support operations at the chip, card and the system levels.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Common On-Chip Processor for Built-In Self-Test Debug Field Support

       This article describes a sophisticated piece of hardware
called COP (Common On-chip Processor), integrated in one physical
macro and responsible for providing the necessary support and control
logic needed to achieve built-in self-tests, power on reset, debug
and field support operations at the chip, card and the system levels.

      The COP executes instructions received from an external
sequencer to perform the following functions at the chip, card and
system levels:
      Self-Test of Chip Internals
           AC and DC logic Self-Test
           Embedded array Self-Test

      The COP controls logic and array self-tests, performed at the
chip and card levels, from start until end.  It allows scanning of
the signature and other essential self-test data (LFSR seed, number
of self-test cycles and status).
      Hardware Reset
           Reset all scan strings to zero.
           Software reset and initialization of embedded
           arrays.

      The COP flushes zeros into the chip scan strings and controls
several modes of embedded array initializations:
           Initialize arrays to zeros.
           Initialize arrays with random data.
           Initialize arrays with data equal to address.
      Debug
           The COP provides the following debug functions:
           STOP code execution.
           STOP after executing N cycles.
           Load and unload scan strings.
           Quiesce DMA (Direct Memory Access) operations.

      The above-listed debug operations are under the direct control
of the COP.  Other supported operations, possibly by loading
appropriate values into the the chip scan strings, include:
           Stop on an instruction address.
           Stop on completion of N cycles following the
           target instruction.
           Single instruction stepping.
           Load and unload single and multiport arrays.
      Interchip Wiring Test
           The COP tests for integrity of interchip wires and
       connections at the card level.  This is a DC test
          that checks for broken wires between chips
          residing on the same card.
      Field Support
           In the field, the COP allows for the following
          diagnostic procedures:
           Unload all scan strings.
           Unload architected arrays and registers.

      The COP processor macro has 70 input and 63 output signals.  It
receives its instructions serially over a 4-bit bus from an off-chip
test sequencer (Fig. 1).  The processor receives the
instructions/data via the SERIAL IN pin and outputs data via the
SERIAL OUT pin.

      The instru...