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Browse Prior Art Database

High-Performance Multi-Chip Carrier

IP.com Disclosure Number: IPCOM000101129D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Curtis, SA: AUTHOR [+3]

Abstract

Disclosed is a method for implementing a high-performance multi-chip carrier with applications in small computer systems. The carrier localizes the wiring complexity needed to interconnect the VLSI chips in such systems, allowing the use of low complexity PC boards for the system electronics.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

High-Performance Multi-Chip Carrier

       Disclosed is a method for implementing a high-performance
multi-chip carrier with applications in small computer systems.  The
carrier localizes the wiring complexity needed to interconnect the
VLSI chips in such systems, allowing the use of low complexity PC
boards for the system electronics.

      As small computer systems, such as personal computers, evolve,
higher levels of processing power are desired.  This performance
increase is being achieved with higher levels of silicon integration
and higher system clock speeds.  These VLSI chips, in turn, require
higher signal I/O packages. With traditional single-chip packages,
the burden of system interconnection and performance falls upon the
PC board. Present interconnection techniques for these high I/O chips
require the second level package (system planar) to be of increasing
complexity. This increase in complexity over the entire system planar
drives up the overall cost of the system.

      The solution disclosed herein to this need for high performance
in small, cost-effective systems is to place the highly integrated
chips (usually a small portion of the total bill of material) in a
relatively complex, high-performance carrier.  This high
complexity/high performance carrier is then attached to a
low-complexity system planar.

      The peripheral I/O, high-performance multi-chip carrier
(module) allows for very high I/O counts, all of which are easily
ac...