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Use of Ram Test Clock Input Pin to Allow Asynchronous Reset Of LSSD Latches Without Using an Additional I/O Pin

IP.com Disclosure Number: IPCOM000101133D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Bilder, MM: AUTHOR [+3]

Abstract

This article describes a technique which allows certain timing critical latches within some very large-scale integration (VLSI) modules to be reset asynchronously without causing level-sensitive scan design (LSSD) rules violations, and without using extra primary input pins.

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Use of Ram Test Clock Input Pin to Allow Asynchronous Reset Of LSSD Latches Without Using an Additional I/O Pin

       This article describes a technique which allows certain
timing critical latches within some very large-scale integration
(VLSI) modules to be reset asynchronously without causing
level-sensitive scan design (LSSD) rules violations, and without
using extra primary input pins.

      An LSSD latch is normally reset by what is commonly known as a
flush reset technique.  This is typically a clock synchronous pulse
that allows the latch to be reset after the next clock occurs.  This
is a 1/2 to 1 clock cycle time delay.  If the latch being reset is
interfacing directly to an asynchronous bus, it is not possible to
meet certain timing requirements of this bus without having a direct
reset of certain timing critical latches.  Flush reset is illustrated
in detail in Fig. 1.

      A method is disclosed herein to utilize the direct reset input
port of an LSSD latch without having to use up the extra primary
input pin that is typically required to satisfy LSSD design rules.
The direct reset port of a latch allows the latch output L1 to be
reset only after the gate delay of the latch following a reset input
stimulus (like an edge-triggered flip-flop).  This method can be used
in any design that makes use of an internal memory bank.

      In the diagram of Fig. 2, the RAM test clock input is a
required chip I/O signal that is necessary in order t...