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Via/Trench Filling And Planarization of Metals Deposited On Organic Insulators

IP.com Disclosure Number: IPCOM000101149D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Baseman, RJ: AUTHOR [+2]

Abstract

Disclosed is a process for filling interlayer vias and trenches and planarizing metal layers, such as copper deposited on organic insulating layers, such as polyimides, for integrated circuit interconnect structures.

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Via/Trench Filling And Planarization of Metals Deposited On Organic Insulators

       Disclosed is a process for filling interlayer vias and
trenches and planarizing metal layers, such as copper deposited on
organic insulating layers, such as polyimides, for integrated circuit
interconnect structures.

      After the deposition of the metal layer by a standard
technique, the metal layer is melted momentarily by a short laser
pulse.  While molten, or nearly so, the high surface tension of the
metal, given relatively low viscosity drives the metal to rapidly
seek a planar surface. (*).

      Although organic insulators may degrade rapidly when exposed to
elevated temperatures, organic insulators may be used as long as the
thermal transients generated by the laser pulse are sufficiently
brief.  The potential for damage to the organic insulator may be
minimized by depositing a thin, electrically and thermally insulating
inorganic layer on the organic insulator.

      Reference
(*)  D. Tuckerman and R. L. Schmitt, Proceedings of the 1985 VLSI
Multilevel Interconnection Conference (V-MIC) IEEE, New York, New
York, 1985, pp. 24-31.