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Intelligent Dram Refresh Controller

IP.com Disclosure Number: IPCOM000101159D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 206K

Publishing Venue

IBM

Related People

Farrell, AE: AUTHOR

Abstract

A requirement for Dynamic Random-Access Memories (DRAMs) is to refresh all rows to guarantee data integrity. A method to minimize this impact on memory subsystem performance was developed. By storing the time and address of prior memory accesses, this method determines if and when refreshing needs to occur. Whenever the maximum time between memory accesses is detected, a refresh occurs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

Intelligent Dram Refresh Controller

       A requirement for Dynamic Random-Access Memories (DRAMs)
is to refresh all rows to guarantee data integrity.  A method to
minimize this impact on memory subsystem performance was developed.
By storing the time and address of prior memory accesses, this method
determines if and when refreshing needs to occur.  Whenever the
maximum time between memory accesses is detected, a refresh occurs.

      DRAM devices, by their nature, require repeated row accesses in
order to maintain stored data.  This requirement is known as
refreshing and more technically referred to as RAS Only Refreshing.
Computer systems which utilize DRAMs as the building blocks for their
memory subsystems must sacrifice system performance to ensure the
DRAMs are refreshed properly in order to maintain data integrity.  An
IBM PC AT*, for example, dedicates approximately 6 percent of its
performance to refreshing.

      This article illustrates a method which reduces this impact
and, under certain maximum utilization conditions, eliminates
refreshing completely.

      This design makes use of the fact that regular or actual data
access to memory will itself cause the accessed row to be refreshed.
Therefore, during 'useful' system activity, the amount of refreshing
taking place may be significantly reduced, or in the cases of maximal
memory usage, refreshing may be skipped completely.  The problem then
becomes one of how to monitor this activity and how to control
refreshing such that it is performed only when absolutely required.

      An Intelligent Refresh Controller (IRC) integrated into a
system architecture provides the necessary monitoring and memory
access controlling to fulfill the refresh requirements.  The IRC
shown in Fig.  1 has a block which monitors the system memory
activity and a separate block to generate refresh timings.  These two
blocks feed a comparator which examines the inputs and determines
whether a refresh cycle should be performed.  If the indicated row
requires refreshing, the comparator signals the remaining block, the
actual refresh request generator, to execute a refresh cycle.  This
is accomplished by utilizing the existing system resources to
initiate the cycle.  A block diagram for this solution is shown in
Fig. 2.

      The functional implementation of each block is as follows:

      The refresh timing generator (RTG) consists of a 17-bit counter
fed by a 10 MHz clock.  The RTG is reset every 8 msec, a time
equal to the maximum interval between row accesses of a given row
address.  (This is the specified maximum for 256Kx4 DRAMs.  The
maximum interval could be adjusted to correspond to the limit of
other DRAMs in a similar fashion.)  The uppermost 15 bits divide the
8 msec into 32768 (32K) unique intervals of 400 nsec each.  These 15
bits then constitute a time ID for each 400 nsec interval.  The lower
two bits are used to generate different states du...