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Hierarchical Delay Predictor And Corrector

IP.com Disclosure Number: IPCOM000101164D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 109K

Publishing Venue

IBM

Related People

Agarawal, B: AUTHOR [+4]

Abstract

This method of generating macro delay equations allows for the precise calculation of the arrival time for a given macro, independent of the output load capacitance values and input signal transitions. This enables the designer to dynamically calculate the slack times when the actual load capacitance and input signal transitions are known. Rules are extracted for a higher level macro from the hierarchy, thus reducing the amount of processing required to span the logic network. This is also useful in placement algorithms because timing becomes a function of input transition values and output load capacitance values that vary as different physical layout combinations are tried.

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Hierarchical Delay Predictor And Corrector

       This method of generating macro delay equations allows
for the precise calculation of the arrival time for a given macro,
independent of the output load capacitance values and input signal
transitions.  This enables the designer to dynamically calculate the
slack times when the actual load capacitance and input signal
transitions are known.  Rules are extracted for a higher level macro
from the hierarchy, thus reducing the amount of processing required
to span the logic network.  This is also useful in placement
algorithms because timing becomes a function of input transition
values and output load capacitance values that vary as different
physical layout combinations are tried.

      The delays and transition times for the primitive macros can be
predicted by assuming initial values for the unknown input
parameters.  The macro coefficients are then calculated with these
assumed values and are then corrected once the actual values are
known.  This procedure combines the accumulated delay terms with the
delay coefficients of the blocks at the last level for which the load
capacitance values are unknown.  Essentially, the delay coefficients
at the macro level are the corrected version of the delay
coefficients of the end blocks at the last levellized rank order
within the macro.

      The blocks within the macro are put in levellized rank order
for processing by using one of the standard scheduling algorithms.
The signals are then propagated in the scheduled order of the blocks.
The arrival times and the transition times are calculated at the
output of each block. The signal propagation is first done at the
primitive level to generate the macro equations.  Then, the macro
equations are generated at the next higher level in the design
hierarchy, and so on.

      The delay and transition times at the output of each gate or
macro are governed by equations of the type
 Tx = A1Tx + A2CTx + A3C2 + A4C + A5 and Dx = A1Tx
+ A2CTx + A3C2  A4C + A5
where the coefficients A1 through A5 are delay equation constants
such as those used by ETEDLTA.  The coefficients are unique to a
given primitive block.  Tx is the input signal transition time and C
is the output net load capacitance.  The form of the above equation
exists for Ton, Toff and Tfo .  These represent the output signal
delays and transitions values for both the rising and falling
signals, respectively.

      For the nth stage, let us define Txn-1 as the input transition
time, and Cn as the load capacitance.  If we let
Rn = (A1 + A2Cn) and Ln = (A3Cn2 + A4Cn + A5, for n
= 1, 2, ..., j where j is the total number of stages in the
path. Assuming Tx0 and Cj are unknown, the successive equations for
Tx1, Tx2, Tx3,..., Txn can be written as follows....