Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Diagnostic Scan Design And Operational Self-Healing With Programmable Logic Cell Arrays

IP.com Disclosure Number: IPCOM000101181D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Ammann, E: AUTHOR [+3]

Abstract

The newly introduced programmable logic cell arrays (PLCAs) permit flexible interconnection (wiring) specifications between logic gates 1 at configuration memory load time (Fig. 1). The interconnection specifications are obtained by FET transfer devices and/or pass- transistors 2 used as wiring switches activated by the on-chip configuration memory cells 3.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Diagnostic Scan Design And Operational Self-Healing With Programmable Logic Cell Arrays

       The newly introduced programmable logic cell arrays
(PLCAs) permit flexible interconnection (wiring) specifications
between logic gates 1 at configuration memory load time (Fig. 1).
The interconnection specifications are obtained by FET transfer
devices and/or pass- transistors 2 used as wiring switches activated
by the on-chip configuration memory cells 3.

      Once the logic of the VLSI PLCA has been configured, there is
no simple means for controlling and observing the testability of
chip-internal flip-flops (FFs) and/or for diagnostic purposes.  One
way of avoiding this problem would be to functionally implement a
scan mechanism based on multiplexing all internal flip-flops to a
chip-external bus. This, however, is not practicable, as it would
consume an intolerable amount of the rather scarce on-chip wiring
channels in the PLCA.

      The proposed solution consisting in incorporating at least
flip- flop observability means for supporting functional diagnostics
is based on the following concept.

      A hardware error condition, for example, a parity check, is
used to capture several internal flip-flops FFi at the time the error
occurs in a first stage (FF-A, Fig. 2) of a scan register of limited
length, say, 8 bits.  The first stage of the scan register is shifted
in parallel to the second stage (FF-B) of the two-level scan register
at the end of the current functional operation, during the execution
of which the error has been detected.  The status content (second
stage of the scan register) is then sensed by a succeeding operation,
while the first stage gets ready to accept new error status
information if the error also occurs during the sense operation.
After saving the status information of the sensed flip-flops in, say,
a service processor diagnostic memory, the status register is set-up
for another capture operation of a new set of flip-flops FFj if the
error reoccurs during functional operation.  For this purpose, the
service processor initiates the reloading of the configuration memory
of the PLCA, specifying the inputs of the scan register to be fed
from the second set of flip-flops FFj of interest before resumption
of the functional operation.  This procedure can be repeated until
all flip-flops of the PLCA chip have been accessed by the service
processor (or any other processing element (PE) in the system
utilized as a service processo...