Browse Prior Art Database

Method for Address Decode for Memory Card

IP.com Disclosure Number: IPCOM000101187D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Prais, MW: AUTHOR

Abstract

This article describes a technique and hardware implementation to decode addresses for a memory card so that the start and stop address of the memory is programmable and various sizes of memory single inline memory modules can be intermixed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Address Decode for Memory Card

       This article describes a technique and hardware
implementation to decode addresses for a memory card so that the
start and stop address of the memory is programmable and various
sizes of memory single inline memory modules can be intermixed.

      The method disclosed herein is used to generate bank selects
for a dynamic RAM (DRAM) system with the following characteristics:
1.   Start address is programmable on 128K boundaries.
2.   Stop address is programmable on 128K boundaries.
3.   Any 128K block of memory in the 0 to 2 Giga byte address range
can be either included or excluded from the address space.  The
address range does not extend to 4 Giga bytes because of hardware
timing constraints.
4.   Various combinations of either 2 Meg, 4 Meg, or 8 Meg memory
single inline memory modules can be used with no changes to the
hardware.
5.   No hardware switches or jumpers are allowed.

      The decode algorithm is shown in Fig. 1.  Programmable array
logic (PAL) is used to generate 1 out of 16 memory BANK SELECT
signals as a function of the BASE ADDRESS and the GROUP SIZE (type of
memory single inline memory modules used) signals.  The BASE ADDRESS
is obtained by subtracting the starting address from the actual
address on the bus and using only address bits 20 to 25 of the
result.  Thus, the BASE ADDRESS will increment each time the actual
bus address goes 1 Meg beyond the start address.  The GROUP SIZE
signals will then determine how many times the BASE ADDRESS
increments before the BANK SELECT signals change.

      The PAL is programmed so that three types of memory single
in...