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Method of Fabricating a New Multi-Layer Stacked Memory Cell Structure

IP.com Disclosure Number: IPCOM000101204D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new method of forming a multi-layer stacked capacitor utilizing the metal-insulator-semiconductor (MIS) diode structure in order to make an electrical contact to the alternating conducting layers of a stacked multi-layer capacitor. The final structure is shown in Fig. 1 and its fabrication procedure is described as follows. (1) After the formation of bitlines and wordlines of the DRAM cell structure using a known MOS process, a bitline insulator oxide is deposited as inter-layer insulating material and is planarized. Contact holes are etched to n+ junction areas which are the drains of the cell access transistors. An n+ polysilicon layer is deposited which also fills the contact holes (n+ layer #1). The n+ polysilicon layer is planarized.

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Method of Fabricating a New Multi-Layer Stacked Memory Cell Structure

       Disclosed is a new method of forming a multi-layer
stacked capacitor utilizing the metal-insulator-semiconductor (MIS)
diode structure in order to make an electrical contact to the
alternating conducting layers of a stacked multi-layer capacitor.
The final structure is shown in Fig. 1 and its fabrication procedure
is described as follows.
 (1)  After the formation of bitlines and wordlines of the DRAM cell
structure using a known MOS process, a bitline insulator oxide is
deposited as inter-layer insulating material and is planarized.
Contact holes are etched to n+ junction areas which are the drains of
the cell access transistors.  An n+ polysilicon layer is deposited
which also fills the contact holes (n+ layer #1).  The n+ polysilicon
layer is planarized.  A thin insulating layer is deposited as a
capacitor dielectric material and is followed by the deposition of p+
polysilicon.  Another capacitor dielectric layer is then deposited.
This sequence of depositing n+ poly, capacitor insulator, p+ poly and
another capacitor insulator can be repeated as many times as
necessary to achieve the desired capacitance in the final structure.
(2)  The stack is etched except the bottom n+ poly layer, following
an appropriate lithographical step.  For the n+/Si02/p+ stack,
multi-step RIE based on chlorine chemistry can be used for the
etching of the stack except the bottom-most Si02 and n+ poly laye...