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Geometry Optimization for Maximum Allowable Placement Error

IP.com Disclosure Number: IPCOM000101214D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 101K

Publishing Venue

IBM

Related People

Corbin, JS: AUTHOR

Abstract

Disclosed is a procedure whereby the geometric parameters within a surface mount or other similar placement system (i.e., pitch, pad width, lead width, etc.) can be selected relative to one another such that the allowable lead-to-pad placement error is maximized.

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Geometry Optimization for Maximum Allowable Placement Error

       Disclosed is a procedure whereby the geometric parameters
within a surface mount or other similar placement system (i.e.,
pitch, pad width, lead width, etc.) can be selected relative to one
another such that the allowable lead-to-pad placement error is
maximized.

      There are two constraints that typically constitute a placement
failure of a surface mount device on a substrate:
(1)  A prescribed minimum portion of the lead must be located within
the pad (typically 50% or more).
(2)  A lead cannot be misregistered from its target pad so far as to
be within a prescribed minimum distance to an adjacent pad
(typically, 3 mil or less).

      These two constraints can be expressed in terms of the
geometric parameters shown in Fig. 1, where Wl is the nominal lead
width, Wp is the nominal pad width, P is the nominal pitch, alpha is
the lead-pad overlap, eps is the lead-pad registration error, and del
is the adjacent conductor clearance.

      Constraint (1) implies that eps1 < gamma +  1/2 Wp where eps1
is the registration error associated with the constraint and gamma is
a constant given by gamma = Wl (1/2 - alpha0) where alpha0 is the
prescribed minimum lead-pad overlap.

      Constraint (2) implies that eps2 < beta -  1/2 Wp where eps2 is
the registration error associated with the constraint and beta is a
constant given by beta = P - 1/2 Wl - del0, where del0 is the
prescribed mini...