Browse Prior Art Database

Single-Chip Implementation of an Interrupt Structure

IP.com Disclosure Number: IPCOM000101225D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 105K

Publishing Venue

IBM

Related People

Paola-Herger, LM: AUTHOR

Abstract

Disclosed is a single-chip implementation of a priority interrupt structure, handling both system bus and local interrupts in two microprocessor environments (Motorola and Intel).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single-Chip Implementation of an Interrupt Structure

       Disclosed is a single-chip implementation of a priority
interrupt structure, handling both system bus and local interrupts in
two microprocessor environments (Motorola and Intel).

      Interrupts are inputs to a central processing unit (CPU) which
allow it to respond to asynchronous events within the system without
polling individual devices. Interrupts are a sub-class of the broader
category termed "exceptions", that is, events which alter the normal
instruction execution within the operating environment. Generally
there is more than one interrupt in a  system, so the problems of
prioritization, enabling/disabling and determination of source are
important and non-trivial.

      This device provides a new approach to prioritization by
providing for a two-tiered system.  For instance, in the Motorola
environment seven primary interrupt levels are allowed.  This device
provides a means (via command) whereby several interrupts existing at
the same primary level can be further prioritized.  This task,
usually reserved for software, provides for a faster response time.

      There are a total of sixteen interrupts possible, seven global
and nine local.  These requests are assigned to seven possible levels
(Motorola) or two levels (Intel). Therefore, two levels of priority
assignment are necessary. The first, or primary, assignment provides
a logical number (0-15) to the physical inputs.  Fifteen is the
highest priority and zero the lowest.  Each interrupt must be
assigned a unique primary level to avoid unpredictable results.  For
instance, IRQ0 can take any primary level from zero to fifteen.  The
secondary assignment is the processor level (1-7 for Motorola;
INTR/NMI for Intel).  This primary/secondary level assignment
resolves the issue of how to handle several interrupts at the same
processor level. For instance, in Motorola mode:
IRQ0 = primary level 1100
Secondary level 0010
IRQ4 = primary level 1000
Secondary level 0010

      IRQ0 will always be serviced first, even though both have been
assigned the same processor priority level, because IRQ0 has a higher
primary level.

      In the Motorola environment, one interrupt acknowledge cycle
occurs in response to each interrupt.  In the Intel environment two
interru...