Browse Prior Art Database

Low Inductance Ceramic Chip Capacitor - Bow-Tie Design

IP.com Disclosure Number: IPCOM000101228D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Morrison, JD: AUTHOR

Abstract

This article describes a low inductance ceramic chip capacitor that provides improved performance by the use of a unique non-shared electrode design.

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This is the abbreviated version, containing approximately 100% of the total text.

Low Inductance Ceramic Chip Capacitor - Bow-Tie Design

       This article describes a low inductance ceramic chip
capacitor that provides improved performance by the use of a unique
non-shared electrode design.

      Low inductance ceramic capacitors are increasingly required for
high-end commercial/military/space computer applications.  The unique
geometry of the contacts (electrode pattern) employed in the
disclosed capacitor design offers a lower inductive path and
significant improvements in capacitor performance in such
applications.

      The electrode shape determined optimum for the chip capacitor
here described is shown in Fig. 1.  Based on current flow
considerations involved in its design and application, this single
electrode pattern simplifies manufacturing processes and costs, and
reduces capacitor mutual and self-inductance by 50%. Metallic
contacts 1, 2 and 3 are applied to the electrode patterns to produce
the four parts 4, 5, 6, and 7 shown in Fig. 2.  These are stack
assembled in sequence, as shown, i.e., 4, 5, 6, 7, etc., repeated
until the electrode assembly is complete.  An end-section view of the
electrode package is shown in Fig. 3.   Adjacent electrode contacts
at each end of the package are connected to a common termination and
each end metallized.  Fig. 4 illustrates the completed low inductance
ceramic capacitor package with metallized end bands for
substrate/board connection.