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Stacked Capacitor DRAM Cell With Vertical Fins (VF-STC)

IP.com Disclosure Number: IPCOM000101238D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 117K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new stacked DRAM cell structure having vertical fins to increase the capacitor area, and methods for fabrication. The new VF-STC cell is arranged such that a vertical fin storage capacitor is built in a stacked position over the access transistor. The stacked capacitance can be adjusted by controlling the height and number of the polysilicon fins. The cell is designed to be built by a fully planarized technology. The vertical fins are formed by side-wall poly-Si and nitride technologies without any additional masking step. The stacked capacitor is built after bitline formation. The new cell can be designed using either open bitline or folded bitline architectures without any additional process modifications. The cross section of a unit cell for the folded bitline architecture is shown in Fig.

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Stacked Capacitor DRAM Cell With Vertical Fins (VF-STC)

       Disclosed is a new stacked DRAM cell structure having
vertical fins to increase the capacitor area, and methods for
fabrication.  The new VF-STC cell is arranged such that a vertical
fin storage capacitor is built in a stacked position over the access
transistor.  The stacked capacitance can be adjusted by controlling
the height and number of the polysilicon fins.  The cell is designed
to be built by a fully planarized technology.  The vertical fins are
formed by side-wall poly-Si and nitride technologies without any
additional masking step.  The stacked capacitor is built after
bitline formation.  The new cell can be designed using either open
bitline or folded bitline architectures without any additional
process modifications. The cross section of a unit cell for the
folded bitline architecture is shown in Fig. 1 and its fabrication
steps are described below for a p-array cell:
(1)  Use standard CMOS processes to form the shallow trench isolation
(STI) regions, the n-well and p-well regions, transfer gate and word
line, and n+ and p+ source/drain junctions.
 (2) Deposit a nitride barrier layer.  Then deposit CVD intrinsic
poly-Si and planarize the poly-Si.  Next, deposit a thin nitride
layer.  Pattern by RIE the nitrice and intrinsic poly to open the
bit-line contacts and storage node connnection regions.  Form the
nitride spacer and deposit p+ poly (or n+poly for n-channel transfer
transistor) and complete the p+ poly-Si plug (Fig. 2).
 (3) Deposit and planarize CVD nitride and CVD oxide. Pattern and
form the bitline and stor...