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PLL Clock Generator With Sector Variable Loop Counter

IP.com Disclosure Number: IPCOM000101248D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Hisano, T: AUTHOR [+2]

Abstract

A Phase Locked Loop (PLL) synthesizer is described which has a variable partitioning counter in the loop. This method is suitable for an accurate clock generator in a hard disk drive (HDD) manufacturing tool. Repeatable flutter of spindle revolution pulses is canceled so that the frequency of the PLL output is stable enough to be used for a read/ write base clock. A motor revolution is detected by optical or magnetic sensors, such as a black and white sectored disk with an optical interrupter or a magnetic clock recorded disk with a magnetic head (Fig. 1).

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PLL Clock Generator With Sector Variable

Loop

Counter

       A Phase Locked Loop (PLL) synthesizer is described which
has a variable partitioning counter in the loop.  This method is
suitable for an accurate clock generator in a hard disk drive (HDD)
manufacturing tool.  Repeatable flutter of spindle revolution pulses
is canceled so that the frequency of the PLL output is stable enough
to be used for a read/ write base clock. A motor revolution is
detected by optical or magnetic sensors, such as a black and white
sectored disk with an optical interrupter or a magnetic clock
recorded disk with a magnetic head (Fig. 1).

      An output signal of the sensor includes the following small
jitter effects on rectangular pulses.
a. Non-repeatable motor wow-flutter at low-mid frequency.
b. Repeatable sensor error by variance of the sector at mid
frequency.
c. Non-repeatable sensor error by random noise at high frequency.

      The objective of this method is to cancel the sensor error and
to generate a stable clock which is finely synchronized with the real
motor revolution including a spectrum of the wow-flutter.  The system
which implements this method is shown in Fig. 2.

      A Phase Detector (PD), Low-Pass Filter (LPF),
Voltage-Controlled Oscillator (VCO), Pre-scaler (PS) and Variable
Loop Counter (VLC) constitute a PLL synthesizer. An input is a motor
revolution sensor signal.  An output is a read/write base clock.  A
pole of the LPF is placed to cut the high frequency sensor error.  A
Micro Processor Unit (MPU) stores the VLC value at every sector.
When the counter value is determined adaptive to the characteristics
of the repeatable sensor error, the output frequency is going to be
stable.  Thus...